TY - GEN
T1 - Enhancing beneficial jitter using phase-shifted clock distribution
AU - Jiao, Dong
AU - Gu, Jie
AU - Jain, Pulkit
AU - Kim, Chris H.
PY - 2008
Y1 - 2008
N2 - Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor.
AB - Clock jitter is generally considered undesirable but recent publications have shown that it can actually improve the timing margin. This paper investigates the "beneficial jitter" effect and presents an accurate analytical model which is verified with HSPICE. Based on our model, a phase-shifted clock distribution technique is proposed to enhance the beneficial jitter effect. By having an optimal phase shift between the supply noise and the clock period, the timing margin can be improved by 2.5X to 15% of the clock period. The benefit of the proposed technique is equivalent to that of having a 5X larger decoupling capacitor.
KW - Clock jitter
KW - Resonant supply noise
UR - http://www.scopus.com/inward/record.url?scp=57549087226&partnerID=8YFLogxK
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U2 - 10.1145/1393921.1393932
DO - 10.1145/1393921.1393932
M3 - Conference contribution
AN - SCOPUS:57549087226
SN - 9781605581095
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 21
EP - 26
BT - ISLPED'08
T2 - ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
Y2 - 11 August 2008 through 13 August 2008
ER -