Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench

Yingyi Luo; Xianshan Wen; Kazutomo Yoshii; Seda Ogrenci Memik; Gokhan Memik; Hal Finkel; Franck Cappello

doi:10.23919/FPL.2017.8056827

Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench

Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

FPGAs are becoming an attractive choice as a heterogeneous computing unit for scientific computing because FPGA vendors are adding floating-point-optimized architectures to their product lines. Additionally, high-level synthesis (HLS) tools such as Altera OpenCL SDK are emerging, which could potentially break the FPGA programming wall and provide a streamlined flow for domain experts in scientific computing. On the other hand, providing high performance in the presence of irregular memory access patterns to off-chip memory remains a challenge for the automated synthesis flows. In this paper, we study the performance/energy characteristics of OpenCL-generated FPGA designs on irregular memory access patterns, targeting XSBench, a memory-intensive Monte Carlo simulation code, as a case study. To complete our study, we implement XSBench in OpenCL and study optimization strategies for FPGAs. We observe that our OpenCL implantation of XSBench achieves 50 % higher energy efficiency on an Intel Arria10-based FPGA platform than that on an Intel Xeon 8-core CPU while trading off 35 % of performance.

Original language	English (US)
Title of host publication	2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
Editors	Diana Gohringer, Dirk Stroobandt, Nele Mentens, Marco Santambrogio, Jari Nurmi
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9789090304281
DOIs	https://doi.org/10.23919/FPL.2017.8056827
State	Published - Oct 2 2017
Event	27th International Conference on Field Programmable Logic and Applications, FPL 2017 - Gent, Belgium Duration: Sep 4 2017 → Sep 6 2017

Publication series

Name	2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017

Other

Other	27th International Conference on Field Programmable Logic and Applications, FPL 2017
Country/Territory	Belgium
City	Gent
Period	9/4/17 → 9/6/17

Funding

ACKNOWLEDGMENTS This work was partially funded by the DOE grant DESC0012531 and the NSF grant CCF-1422489. This material was based upon work supported by the U.S. Department of Energy Office of Science, under contract DE-AC02-06CH11357.

ASJC Scopus subject areas

Computer Networks and Communications
Computer Science Applications
Hardware and Architecture
Software

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.23919/FPL.2017.8056827

Cite this

Luo, Y., Wen, X., Yoshii, K., Memik, S. O., Memik, G., Finkel, H., & Cappello, F. (2017). Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. In D. Gohringer, D. Stroobandt, N. Mentens, M. Santambrogio, & J. Nurmi (Eds.), 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017 Article 8056827 (2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/FPL.2017.8056827

Luo, Yingyi ; Wen, Xianshan ; Yoshii, Kazutomo et al. / Evaluating irregular memory access on OpenCL FPGA platforms : A case study with XSBench. 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. editor / Diana Gohringer ; Dirk Stroobandt ; Nele Mentens ; Marco Santambrogio ; Jari Nurmi. Institute of Electrical and Electronics Engineers Inc., 2017. (2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017).

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title = "Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench",

abstract = "FPGAs are becoming an attractive choice as a heterogeneous computing unit for scientific computing because FPGA vendors are adding floating-point-optimized architectures to their product lines. Additionally, high-level synthesis (HLS) tools such as Altera OpenCL SDK are emerging, which could potentially break the FPGA programming wall and provide a streamlined flow for domain experts in scientific computing. On the other hand, providing high performance in the presence of irregular memory access patterns to off-chip memory remains a challenge for the automated synthesis flows. In this paper, we study the performance/energy characteristics of OpenCL-generated FPGA designs on irregular memory access patterns, targeting XSBench, a memory-intensive Monte Carlo simulation code, as a case study. To complete our study, we implement XSBench in OpenCL and study optimization strategies for FPGAs. We observe that our OpenCL implantation of XSBench achieves 50 % higher energy efficiency on an Intel Arria10-based FPGA platform than that on an Intel Xeon 8-core CPU while trading off 35 % of performance.",

author = "Yingyi Luo and Xianshan Wen and Kazutomo Yoshii and Memik, {Seda Ogrenci} and Gokhan Memik and Hal Finkel and Franck Cappello",

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Luo, Y, Wen, X, Yoshii, K, Memik, SO, Memik, G, Finkel, H & Cappello, F 2017, Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. in D Gohringer, D Stroobandt, N Mentens, M Santambrogio & J Nurmi (eds), 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017., 8056827, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Institute of Electrical and Electronics Engineers Inc., 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Gent, Belgium, 9/4/17. https://doi.org/10.23919/FPL.2017.8056827

Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. / Luo, Yingyi; Wen, Xianshan; Yoshii, Kazutomo et al.
2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. ed. / Diana Gohringer; Dirk Stroobandt; Nele Mentens; Marco Santambrogio; Jari Nurmi. Institute of Electrical and Electronics Engineers Inc., 2017. 8056827 (2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Luo, Yingyi

AU - Wen, Xianshan

AU - Yoshii, Kazutomo

AU - Memik, Seda Ogrenci

AU - Memik, Gokhan

AU - Finkel, Hal

AU - Cappello, Franck

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AB - FPGAs are becoming an attractive choice as a heterogeneous computing unit for scientific computing because FPGA vendors are adding floating-point-optimized architectures to their product lines. Additionally, high-level synthesis (HLS) tools such as Altera OpenCL SDK are emerging, which could potentially break the FPGA programming wall and provide a streamlined flow for domain experts in scientific computing. On the other hand, providing high performance in the presence of irregular memory access patterns to off-chip memory remains a challenge for the automated synthesis flows. In this paper, we study the performance/energy characteristics of OpenCL-generated FPGA designs on irregular memory access patterns, targeting XSBench, a memory-intensive Monte Carlo simulation code, as a case study. To complete our study, we implement XSBench in OpenCL and study optimization strategies for FPGAs. We observe that our OpenCL implantation of XSBench achieves 50 % higher energy efficiency on an Intel Arria10-based FPGA platform than that on an Intel Xeon 8-core CPU while trading off 35 % of performance.

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Luo Y, Wen X, Yoshii K, Memik SO, Memik G, Finkel H et al. Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. In Gohringer D, Stroobandt D, Mentens N, Santambrogio M, Nurmi J, editors, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 8056827. (2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017). doi: 10.23919/FPL.2017.8056827

Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench

Abstract

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UN SDGs

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