Evaluating the effects of cache redundancy on profit

Abhishek Das*, Berkin Ozisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok Nidhi Choudhary

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Previous works in computer architecture have mostly neglected revenue and/or profit, key factors driving any design decision. In this paper, we evaluate architectural techniques to optimize for revenue/profit. The continual trend of technology scaling and sub-wavelength lithography has caused transistor feature sizes to shrink into the nanoscale range. As a result, the effects of process variations on critical path delay and chip yields have amplified. A common concept to remedy the effects of variations is speed-binning, by which chips from a single batch are rated by a discrete range of frequencies and sold at different prices. An efficient binning distribution thus decides the profitability of the chip manufacturer. We propose and evaluate a cache-redundancy scheme called substitute cache, which allows the chip manufacturers to modify the number of chips in different bins. Particularly, this technique introduces a small fully associative array associated with each cache way to replicate the data elements that will be stored in the high latency lines, and hence can be effectively used to boost up the overall chip yield and also shift the chip binning distribution towards higher frequencies. We also develop models based on linear regression and neural networks to accurately estimate the chip prices from their architectural configurations. Using these estimation models, we find that our substitute cache scheme can potentially increase the revenue for the batch of chips by as much as 13.1%.

Original languageEnglish (US)
Title of host publication2008 Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-41
Pages388-398
Number of pages11
Edition2008 PROCEEDINGS
DOIs
StatePublished - Dec 1 2008
Event2008 - 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-41 - Lake Como, Italy
Duration: Nov 8 2008Nov 12 2008

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
Number2008 PROCEEDINGS
ISSN (Print)1072-4451

Other

Other2008 - 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-41
CountryItaly
CityLake Como
Period11/8/0811/12/08

Keywords

  • Cache Architecture
  • Device Variability
  • Fault-tolerance
  • Process Variations
  • Profit and Revenue

ASJC Scopus subject areas

  • Hardware and Architecture

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