Power efficiency is becoming an increasingly important design aspect for FPGAs. Recently it has been shown that well-known power minimization techniques in the ASICs such as creating supply voltage (V dd) scalable islands of different granularity can be applied to FPGAs. However, the discrete routing architecture of FPGAs amplifies any constraint imposed on the placement stage. In this work, we evaluate the overheads of voltage scaling schemes in relation to FPGA architectures and design flows in terms of critical path delay, channel-width and area/delay product. We present a detailed evaluation of the impact of alternative realizations of voltage scaling schemes onto the physical design flow of FPGAs and show that as high as 47% dynamic power gain is possible with 17% area/delay product penalty and 30% power gain is possible with as low as 6% area/delay product penalty for different voltage island configurations.