Exact gate decomposition algorithm for low-power technology mapping

Hai Zhou*, D. F. Wong

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implementation. In the literature, only heuristic algorithms are given for the low-power gate decomposition problem. In this paper, we prove many properties an optimal decomposition tree must have. Based on these optimality properties, we design an efficient exact algorithm to solve the low-power gate decomposition problem. Moreover, the exact algorithm can be easily modified to a heuristic algorithm which performs much better than the known heuristics.

Original languageEnglish (US)
Pages (from-to)575-580
Number of pages6
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
StatePublished - Dec 1 1997

ASJC Scopus subject areas

  • Software

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