Exploiting locality to improve circuit-level timing speculation

Jing Xin*, Russell E Joseph

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins, eliminating power and performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. This work has not evaluated or exploited the disparity of error rates at the level of static instructions. In this paper, we demonstrate pronounced locality in error rates at the level of static instructions. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and reduce the costly recovery penalty. This allows us to achieve 43.6 power savings when compared to a baseline policy and incurs only 6.9 performance penalty.

Original languageEnglish (US)
Article number5300797
Pages (from-to)40-43
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number2
StatePublished - Feb 2010


  • Error locality
  • Low-power design
  • Reliability.
  • Timing speculation

ASJC Scopus subject areas

  • Hardware and Architecture


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