Abstract
Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins, eliminating power and performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. This work has not evaluated or exploited the disparity of error rates at the level of static instructions. In this paper, we demonstrate pronounced locality in error rates at the level of static instructions. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and reduce the costly recovery penalty. This allows us to achieve 43.6 power savings when compared to a baseline policy and incurs only 6.9 performance penalty.
Original language | English (US) |
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Article number | 5300797 |
Pages (from-to) | 40-43 |
Number of pages | 4 |
Journal | IEEE Computer Architecture Letters |
Volume | 8 |
Issue number | 2 |
DOIs | |
State | Published - Feb 2010 |
Funding
Manuscript submitted: 17-Sep-2009. Manuscript accepted: 08-Oct-2009. Final manuscript received: 15-Oct-2009. We thank the anonymous reviewers for their constructive feedback. This work was supported by NSF awards CAREER CCF-0644332 and CNS-0720820.
Keywords
- Error locality
- Low-power design
- Reliability.
- Timing speculation
ASJC Scopus subject areas
- Hardware and Architecture