Exploiting multi-grained parallelism in reconfigurable SBC architectures

Joseph Zambreno*, Dan Honbo, Alok Choudhary

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In recent years, reconfigurable technology has emerged as a popular choice for implementing various types of cryptographic functions. Nevertheless, an insufficient amount effort has been placed into fully exploiting the tremendous amounts of parallelism intrinsic to FPGAs for this class of algorithms. In this paper, we focus on block cipher architectures and explore design decisions that leverage the multi-grained parallelism inherent in many of these algorithms. We demonstrate the usefulness of this approach with a highly parallel FPGA implementation of the AES standard, and present results detailing the area/delay tradeoffs resulting from our design decisions.

Original languageEnglish (US)
Title of host publicationProceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005
Pages333-334
Number of pages2
DOIs
StatePublished - Dec 1 2005
Event13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005 - Napa, CA, United States
Duration: Apr 18 2005Apr 20 2005

Publication series

NameProceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005
Volume2005

Other

Other13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005
CountryUnited States
CityNapa, CA
Period4/18/054/20/05

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Exploiting multi-grained parallelism in reconfigurable SBC architectures'. Together they form a unique fingerprint.

Cite this