Exploration of design space and runtime optimization for affective computing in machine learning empowered ultra-low power SoC

Yijie Wei; Kofi Otseidu; Jie Gu

doi:10.1109/DAC18072.2020.9218583

Exploration of design space and runtime optimization for affective computing in machine learning empowered ultra-low power SoC

Yijie Wei, Kofi Otseidu, Jie Gu

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The incorporation of artificial intelligence into the rapidly growing IoT devices demands a high level of built-in intelligence, e.g. machine learning capability at the device level. Affective computing offers a new degree of cognitive intelligence into edge processing IoT devices by inferring human emotion, stress levels for intelligent human assistance. This work explores the design space and runtime optimization opportunity for affective computing at the system-on-chip (SoC) level. A design optimization methodology for the neural network classifier and runtime power management schemes are proposed to achieve high energy efficiency on embedded low power devices. A test chip based on a 65nm CMOS process was used to demonstrate the proposed methodology on emotion and stress classification for affective computing. An average power saving of 45% is achieved with a peak power savings of 60% from the proposed emotion-driven adaptive power management scheme.

Original language	English (US)
Title of host publication	2020 57th ACM/IEEE Design Automation Conference, DAC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450367257
DOIs	https://doi.org/10.1109/DAC18072.2020.9218583
State	Published - Jul 2020
Event	57th ACM/IEEE Design Automation Conference, DAC 2020 - Virtual, San Francisco, United States Duration: Jul 20 2020 → Jul 24 2020

Publication series

Name	Proceedings - Design Automation Conference
Volume	2020-July
ISSN (Print)	0738-100X

Conference

Conference	57th ACM/IEEE Design Automation Conference, DAC 2020
Country/Territory	United States
City	Virtual, San Francisco
Period	7/20/20 → 7/24/20

Funding

uses a 20% duty cycle with 72% accuracy leading to 60% power this paper explores the design space and optimization techniques reduction. In Driver case, the continuous run achieves 75% fordesigning dedicated ASICchips. Anoptimizationschemeis accuracy inthecitycondition, whilethedutycyclemodeof50% proposed todelivertheoptimalneuralnetwork topographyaswell and 20% are used in the highway and rest respectfully. The as improving the power efficiency of feature extraction. Power accuracy inthese casesare73%and70%. managementtechniquesalongwithvotingtechniquesareproposed Fig. 11 shows the measured sampling & classification to obtain the optimal tradeoff between power consumption and waveformson two databasescases.IntheDriverdatabasecases, accuracy. An emotion-drivenadaptivepowermanagementscheme the chip was set on continues mode on initial state and City state. is also proposed to provide runtime optimization for the energy AfterHighwaystatewasclassified,thechipworked on 50%duty efficiency ofaffectivecomputing. A65nmCMOStestchipwas cyclemode, then20%duty cyclewhenRestwassensed.Inthe used todemonstratetheproposedtechniqueshowing30%to60% Dreamerdatabasecase, theinitialandexcitementstatewassetin reduction onthepowerconsumption basedon thesensedemotion continuous mode. The 20% duty cycle mode was set when of the users. Calmnesswasdetected.When fatiguewassensed, thedutycycle ACKNOWLEDGEMENT wasshifted back to60%. This work was supported in part by the National Science Foundation under grant number CNS-1816870.

Keywords

Affective Computing
Embedded Device
Internet-of-Things
Neural Network Accelerator
Stress and Mood Classification

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/DAC18072.2020.9218583

Cite this

Wei, Y., Otseidu, K., & Gu, J. (2020). Exploration of design space and runtime optimization for affective computing in machine learning empowered ultra-low power SoC. In 2020 57th ACM/IEEE Design Automation Conference, DAC 2020 Article 9218583 (Proceedings - Design Automation Conference; Vol. 2020-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DAC18072.2020.9218583

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title = "Exploration of design space and runtime optimization for affective computing in machine learning empowered ultra-low power SoC",

abstract = "The incorporation of artificial intelligence into the rapidly growing IoT devices demands a high level of built-in intelligence, e.g. machine learning capability at the device level. Affective computing offers a new degree of cognitive intelligence into edge processing IoT devices by inferring human emotion, stress levels for intelligent human assistance. This work explores the design space and runtime optimization opportunity for affective computing at the system-on-chip (SoC) level. A design optimization methodology for the neural network classifier and runtime power management schemes are proposed to achieve high energy efficiency on embedded low power devices. A test chip based on a 65nm CMOS process was used to demonstrate the proposed methodology on emotion and stress classification for affective computing. An average power saving of 45% is achieved with a peak power savings of 60% from the proposed emotion-driven adaptive power management scheme.",

keywords = "Affective Computing, Embedded Device, Internet-of-Things, Neural Network Accelerator, Stress and Mood Classification",

author = "Yijie Wei and Kofi Otseidu and Jie Gu",

note = "Funding Information: uses a 20% duty cycle with 72% accuracy leading to 60% power this paper explores the design space and optimization techniques reduction. In Driver case, the continuous run achieves 75% fordesigning dedicated ASICchips. Anoptimizationschemeis accuracy inthecitycondition, whilethedutycyclemodeof50% proposed todelivertheoptimalneuralnetwork topographyaswell and 20% are used in the highway and rest respectfully. The as improving the power efficiency of feature extraction. Power accuracy inthese casesare73%and70%. managementtechniquesalongwithvotingtechniquesareproposed Fig. 11 shows the measured sampling & classification to obtain the optimal tradeoff between power consumption and waveformson two databasescases.IntheDriverdatabasecases, accuracy. An emotion-drivenadaptivepowermanagementscheme the chip was set on continues mode on initial state and City state. is also proposed to provide runtime optimization for the energy AfterHighwaystatewasclassified,thechipworked on 50%duty efficiency ofaffectivecomputing. A65nmCMOStestchipwas cyclemode, then20%duty cyclewhenRestwassensed.Inthe used todemonstratetheproposedtechniqueshowing30%to60% Dreamerdatabasecase, theinitialandexcitementstatewassetin reduction onthepowerconsumption basedon thesensedemotion continuous mode. The 20% duty cycle mode was set when of the users. Calmnesswasdetected.When fatiguewassensed, thedutycycle ACKNOWLEDGEMENT wasshifted back to60%. This work was supported in part by the National Science Foundation under grant number CNS-1816870. Publisher Copyright: {\textcopyright} 2020 IEEE.; 57th ACM/IEEE Design Automation Conference, DAC 2020 ; Conference date: 20-07-2020 Through 24-07-2020",

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Wei, Y, Otseidu, K & Gu, J 2020, Exploration of design space and runtime optimization for affective computing in machine learning empowered ultra-low power SoC. in 2020 57th ACM/IEEE Design Automation Conference, DAC 2020., 9218583, Proceedings - Design Automation Conference, vol. 2020-July, Institute of Electrical and Electronics Engineers Inc., 57th ACM/IEEE Design Automation Conference, DAC 2020, Virtual, San Francisco, United States, 7/20/20. https://doi.org/10.1109/DAC18072.2020.9218583

Exploration of design space and runtime optimization for affective computing in machine learning empowered ultra-low power SoC. / Wei, Yijie; Otseidu, Kofi; Gu, Jie.
2020 57th ACM/IEEE Design Automation Conference, DAC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9218583 (Proceedings - Design Automation Conference; Vol. 2020-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: uses a 20% duty cycle with 72% accuracy leading to 60% power this paper explores the design space and optimization techniques reduction. In Driver case, the continuous run achieves 75% fordesigning dedicated ASICchips. Anoptimizationschemeis accuracy inthecitycondition, whilethedutycyclemodeof50% proposed todelivertheoptimalneuralnetwork topographyaswell and 20% are used in the highway and rest respectfully. The as improving the power efficiency of feature extraction. Power accuracy inthese casesare73%and70%. managementtechniquesalongwithvotingtechniquesareproposed Fig. 11 shows the measured sampling & classification to obtain the optimal tradeoff between power consumption and waveformson two databasescases.IntheDriverdatabasecases, accuracy. An emotion-drivenadaptivepowermanagementscheme the chip was set on continues mode on initial state and City state. is also proposed to provide runtime optimization for the energy AfterHighwaystatewasclassified,thechipworked on 50%duty efficiency ofaffectivecomputing. A65nmCMOStestchipwas cyclemode, then20%duty cyclewhenRestwassensed.Inthe used todemonstratetheproposedtechniqueshowing30%to60% Dreamerdatabasecase, theinitialandexcitementstatewassetin reduction onthepowerconsumption basedon thesensedemotion continuous mode. The 20% duty cycle mode was set when of the users. Calmnesswasdetected.When fatiguewassensed, thedutycycle ACKNOWLEDGEMENT wasshifted back to60%. This work was supported in part by the National Science Foundation under grant number CNS-1816870. Publisher Copyright: © 2020 IEEE.

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AB - The incorporation of artificial intelligence into the rapidly growing IoT devices demands a high level of built-in intelligence, e.g. machine learning capability at the device level. Affective computing offers a new degree of cognitive intelligence into edge processing IoT devices by inferring human emotion, stress levels for intelligent human assistance. This work explores the design space and runtime optimization opportunity for affective computing at the system-on-chip (SoC) level. A design optimization methodology for the neural network classifier and runtime power management schemes are proposed to achieve high energy efficiency on embedded low power devices. A test chip based on a 65nm CMOS process was used to demonstrate the proposed methodology on emotion and stress classification for affective computing. An average power saving of 45% is achieved with a peak power savings of 60% from the proposed emotion-driven adaptive power management scheme.

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KW - Embedded Device

KW - Internet-of-Things

KW - Neural Network Accelerator

KW - Stress and Mood Classification

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ER -

Exploration of design space and runtime optimization for affective computing in machine learning empowered ultra-low power SoC

Abstract

Publication series

Conference

Funding

Keywords

ASJC Scopus subject areas

UN SDGs

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