Exploration of pipelined FPGA interconnect structures

Akshay Sharma; Katherine Compton; Carl Ebeling; Scott Hauck

doi:10.1145/968280.968284

Exploration of pipelined FPGA interconnect structures

Akshay Sharma^*, Katherine Compton, Carl Ebeling, Scott Hauck

^*Corresponding author for this work

Computer Science

Research output: Contribution to conference › Paper › peer-review

18 Scopus citations

Abstract

In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered 10 terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.

Original language	English (US)
Pages	13-22
Number of pages	10
DOIs	https://doi.org/10.1145/968280.968284
State	Published - 2004
Event	ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004 - Monterey, CA., United States Duration: Feb 22 2004 → Feb 24 2004

Conference

Conference	ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004
Country/Territory	United States
City	Monterey, CA.
Period	2/22/04 → 2/24/04

Keywords

Architecture explorations
PipeRoute
Pipelined FPGA
Pipelined interconnect
Registered routing

ASJC Scopus subject areas

Computer Science(all)

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10.1145/968280.968284

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abstract = "In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered 10 terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.",

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author = "Akshay Sharma and Katherine Compton and Carl Ebeling and Scott Hauck",

note = "Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004 ; Conference date: 22-02-2004 Through 24-02-2004",

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AU - Sharma, Akshay

AU - Compton, Katherine

AU - Ebeling, Carl

AU - Hauck, Scott

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AB - In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered 10 terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.

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KW - Pipelined FPGA

KW - Pipelined interconnect

KW - Registered routing

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Exploration of pipelined FPGA interconnect structures

Abstract

Conference

Keywords

ASJC Scopus subject areas

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