Exploration of pipelined FPGA interconnect structures

Akshay Sharma*, Katherine Compton, Carl Ebeling, Scott Hauck

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

17 Scopus citations

Abstract

In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered 10 terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.

Original languageEnglish (US)
Pages13-22
Number of pages10
DOIs
StatePublished - 2004
EventACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004 - Monterey, CA., United States
Duration: Feb 22 2004Feb 24 2004

Conference

ConferenceACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004
CountryUnited States
CityMonterey, CA.
Period2/22/042/24/04

Keywords

  • Architecture explorations
  • Pipelined FPGA
  • Pipelined interconnect
  • PipeRoute
  • Registered routing

ASJC Scopus subject areas

  • Computer Science(all)

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