Advanced nanoscale Very Large Scale Integrated (VLSI) circuits are facing significant timing closure challenges especially due to random on-chip threshold voltage variation. When dealing with the exaggerated timing issues in nanoscale technologies, conventional use of design guard-band significantly trade off the performance while more sophisticated statistical based timing analysis often requires expensive verification effort. The recent development of emerging non-volatile resistive device provides a potential new paradigm for solving the current design dilemma, i.e. balance between performance and design margin. This paper explores a new application of the emerging memristor. By deploying a self-tuning memristor into the sequential circuits, we show that the circuits could heal itself under excessive process variation and thus reduce the required design margin. A new design methodology is proposed to incorporate the use of self-tuning. A pipelined FFT processor in 45nm technology was implemented as a demonstration of the proposed circuits and design methodology.