@inproceedings{bee060b73649447ebc5caa2ccc6edc24,
title = "Exploring circuit timing-aware language and compilation",
abstract = "By adjusting the design of the ISA and enabling circuit timingsensitive optimizations in a compiler, we can more effectively exploit timing speculation. While there has been growing interest in systems that leverage circuit-level timing speculation to improve the performance and power-efficiency of processors, most of the innovation has been at the microarchitectural level. We make the observation that some code sequences place greater demand on circuit timing deadlines than others. Furthermore, by selectively replacing these codes with instruction sequences which are semantically equivalent but reduce activity on timing critical circuit paths, we can trigger fewer timing errors and hence reduce recovery costs.",
keywords = "Compiler, ISA design, Timing speculation",
author = "Giang Hoang and Robert Findler and Joseph, {Russell E}",
year = "2011",
doi = "10.1145/1950365.1950405",
language = "English (US)",
isbn = "9781450302661",
series = "International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS",
pages = "345--355",
booktitle = "ASPLOS XVI - 16th International Conference on Architectural Support for Programming Languages and Operating Systems",
note = "16th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2011 ; Conference date: 05-03-2011 Through 11-03-2011",
}