Exploring circuit timing-aware language and compilation

Giang Hoang*, Robert Findler, Russell E Joseph

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations

Abstract

By adjusting the design of the ISA and enabling circuit timingsensitive optimizations in a compiler, we can more effectively exploit timing speculation. While there has been growing interest in systems that leverage circuit-level timing speculation to improve the performance and power-efficiency of processors, most of the innovation has been at the microarchitectural level. We make the observation that some code sequences place greater demand on circuit timing deadlines than others. Furthermore, by selectively replacing these codes with instruction sequences which are semantically equivalent but reduce activity on timing critical circuit paths, we can trigger fewer timing errors and hence reduce recovery costs.

Original languageEnglish (US)
Title of host publicationASPLOS XVI - 16th International Conference on Architectural Support for Programming Languages and Operating Systems
Pages345-355
Number of pages11
DOIs
StatePublished - Mar 31 2011
Event16th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2011 - Newport Beach, CA, United States
Duration: Mar 5 2011Mar 11 2011

Publication series

NameInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Other

Other16th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2011
CountryUnited States
CityNewport Beach, CA
Period3/5/113/11/11

Keywords

  • Compiler
  • ISA design
  • Timing speculation

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture

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