Exploring circuit timing-aware language and compilation

Giang Hoang*, Robert Bruce Findler, Russ Joseph

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


By adjusting the design of the ISA and enabling circuit timingsensitive optimizations in a compiler, we can more effectively exploit timing speculation. While there has been growing interest in systems that leverage circuit-level timing speculation to improve the performance and power-efficiency of processors, most of the innovation has been at the microarchitectural level. We make the observation that some code sequences place greater demand on circuit timing deadlines than others. Furthermore, by selectively replacing these codes with instruction sequences which are semantically equivalent but reduce activity on timing critical circuit paths, we can trigger fewer timing errors and hence reduce recovery costs.

Original languageEnglish (US)
Pages (from-to)345-355
Number of pages11
JournalACM SIGPLAN Notices
Issue number4
StatePublished - Jun 1 2012


  • Compiler
  • ISA design
  • Timing speculation

ASJC Scopus subject areas

  • Computer Science(all)


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