Fabrication and characterization of p-type double gate and single gate junctionless silicon nanowire transistor by atomic force microscopy nanolithography

The fabrication of Double gate (DG) and Single gate (SG) Junctionless silicon nanowire transistor (JLSNWT) was investigated in this research. The transistors used silicon nanowire patterned on lightly doped (105 cm^-3) p-type silicon-on-insulator (SOI) wafer fabricated with an atomic force microscope (AFM) nanolithography technique. The top Si layer has a thickness of 90 nm and a resistivity (p) of 13.5-22.5 Ω cm. The modified RCA method implemented for sample preparation. The local anodic oxidation (LAO) followed by two wet etching steps, KOH etching for Si removal and HF etching for oxide removal, have implemented to reach the structures. The writing speed and applied tip voltage were held in 0.6 μm/s and 8.5 volt respectively. Scan speed was held in 1.0 μm/s. The etching processes were elaborately optimized by 30% wt. KOH + 10% vol. IPA in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied and made a sufficiently large barrier in the gating region. Negative gate voltage is unable to make significant effect on drain current to drive the device into accumulation mode.