Fast estimation of timing yield bounds for process variations

Ruiming Chen*, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max" operation are actually not satisfied in the moment matching based statistical timing analysis approaches. We propose two correlationaware block-based statistical timing analysis approaches that keep these necessary conditions, and show that our approaches always achieve the lower bound and the upper bound on the timing yield. Our approach combining with moment-matching based statistical static timing analysis (SSTA) approaches can efficiently estimate the maximal possible errors of moment-matching-based SSTA approaches.

Original languageEnglish (US)
Article number4453949
Pages (from-to)241-248
Number of pages8
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
StatePublished - Mar 2008


  • Process variations
  • Statistical static timing analysis (SSTA)
  • Statistical timing

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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