Embedded systems designers frequently avoid using floating-point computation because it is too costly to include a floating-point unit (FPU) in an embedded processor. However, the performance of software floating-point libraries can be lacking. Therefore we propose a Fractured Floating Point Unit (FFPU) - a hybrid solution using a mix of custom hardware instructions and software code. An FFPU is designed as a compromise between software libraries and custom FPUs in both area and performance. We present three 32-bit FFPUs designs for a Nios II soft processor, and compare their performance and area to the baseline Nios II and a Nios II with a complete FPU. The FFPUs improve floating-point addition and subtraction performance by 24 to 52 percent over the baseline, with an ALM increase of only 12 to 32 percent, and no increase in DSP blocks.