Abstract
FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.
Original language | English (US) |
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Title of host publication | GLSVSI'05 - Proceedings of the 2005 ACM Great |
Pages | 238-243 |
Number of pages | 6 |
State | Published - Dec 29 2005 |
Event | 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States Duration: Apr 17 2005 → Apr 19 2005 |
Other
Other | 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 |
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Country | United States |
City | Chicago, IL |
Period | 4/17/05 → 4/19/05 |
Keywords
- FPGA
- Hierarchical LUT
- Leakage power
- Low power
ASJC Scopus subject areas
- Engineering(all)