Fine-grain leakage optimization in SRAM based FPGAs

Somsubhra Mondal; Seda Ogrenci Memik

Fine-grain leakage optimization in SRAM based FPGAs

Somsubhra Mondal^*, Seda Ogrenci Memik

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.

Original language	English (US)
Title of host publication	GLSVSI'05 - Proceedings of the 2005 ACM Great
Pages	238-243
Number of pages	6
State	Published - Dec 29 2005
Event	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States Duration: Apr 17 2005 → Apr 19 2005

Other

Other	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
Country/Territory	United States
City	Chicago, IL
Period	4/17/05 → 4/19/05

Keywords

FPGA
Hierarchical LUT
Leakage power
Low power

ASJC Scopus subject areas

General Engineering

Cite this

@inproceedings{ee2090fd27f64c718ad1d0317a148fde,

title = "Fine-grain leakage optimization in SRAM based FPGAs",

abstract = "FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47\% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94\% (as high as 64.22\%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.",

keywords = "FPGA, Hierarchical LUT, Leakage power, Low power",

author = "Somsubhra Mondal and Memik, \{Seda Ogrenci\}",

year = "2005",

month = dec,

day = "29",

language = "English (US)",

pages = "238--243",

booktitle = "GLSVSI'05 - Proceedings of the 2005 ACM Great",

note = "2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 ; Conference date: 17-04-2005 Through 19-04-2005",

}

TY - GEN

T1 - Fine-grain leakage optimization in SRAM based FPGAs

AU - Mondal, Somsubhra

AU - Memik, Seda Ogrenci

PY - 2005/12/29

Y1 - 2005/12/29

N2 - FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.

AB - FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.

KW - FPGA

KW - Hierarchical LUT

KW - Leakage power

KW - Low power

UR - http://www.scopus.com/inward/record.url?scp=29244456473&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=29244456473&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:29244456473

SP - 238

EP - 243

BT - GLSVSI'05 - Proceedings of the 2005 ACM Great

T2 - 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05

Y2 - 17 April 2005 through 19 April 2005

ER -

Fine-grain leakage optimization in SRAM based FPGAs

Abstract

Other

Keywords

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this