Fine-grain leakage optimization in SRAM based FPGAs

Somsubhra Mondal*, Seda Ogrenci Memik

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.

Original languageEnglish (US)
Title of host publicationGLSVSI'05 - Proceedings of the 2005 ACM Great
Pages238-243
Number of pages6
StatePublished - Dec 29 2005
Event2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
Duration: Apr 17 2005Apr 19 2005

Other

Other2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
CountryUnited States
CityChicago, IL
Period4/17/054/19/05

Keywords

  • FPGA
  • Hierarchical LUT
  • Leakage power
  • Low power

ASJC Scopus subject areas

  • Engineering(all)

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