Fine-grain voltage tuned cache architecture for yield management under process variations

Joonho Kong*, Yan Pan, Serkan Ozdemir, Anitha Mohan, Gokhan Memik, Sung Woo Chung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.

Original languageEnglish (US)
Article number5936660
Pages (from-to)1532-1536
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number8
StatePublished - 2012


  • Cache
  • process variation
  • selective wordline voltage boosting
  • supply voltage lowering
  • yield

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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