TY - GEN
T1 - Flexible routing architecture generation for domain-specific reconfigurable subsystems
AU - Compton, Katherine
AU - Sharma, Akshay
AU - Phillips, Shawn
AU - Hauck, Scott
PY - 2002
Y1 - 2002
N2 - Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides hardware speeds as well as the benefits of post-fabrication modification. However, not all applications are equally suited to any one reconfigurable architecture. Therefore, the Totem Project focuses on the automatic generation of customized reconfigurable hardware. This paper details our first attempts at the design of algorithms for automatic generation of customized flexible routing architectures. We show that these algorithms provide results with a low area overhead compared to the custom-designed RaPiD routing architecture, as well as the flexibility needed to handle some application modifications.
AB - Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides hardware speeds as well as the benefits of post-fabrication modification. However, not all applications are equally suited to any one reconfigurable architecture. Therefore, the Totem Project focuses on the automatic generation of customized reconfigurable hardware. This paper details our first attempts at the design of algorithms for automatic generation of customized flexible routing architectures. We show that these algorithms provide results with a low area overhead compared to the custom-designed RaPiD routing architecture, as well as the flexibility needed to handle some application modifications.
UR - http://www.scopus.com/inward/record.url?scp=79955159410&partnerID=8YFLogxK
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U2 - 10.1007/3-540-46117-5_8
DO - 10.1007/3-540-46117-5_8
M3 - Conference contribution
AN - SCOPUS:79955159410
SN - 3540441085
SN - 9783540441083
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 59
EP - 68
BT - Field-Programmable Logic and Applications
PB - Springer Verlag
ER -