Flexible routing architecture generation for domain-specific reconfigurable subsystems

Katherine Compton*, Akshay Sharma, Shawn Phillips, Scott Hauck

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations


Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides hardware speeds as well as the benefits of post-fabrication modification. However, not all applications are equally suited to any one reconfigurable architecture. Therefore, the Totem Project focuses on the automatic generation of customized reconfigurable hardware. This paper details our first attempts at the design of algorithms for automatic generation of customized flexible routing architectures. We show that these algorithms provide results with a low area overhead compared to the custom-designed RaPiD routing architecture, as well as the flexibility needed to handle some application modifications.

Original languageEnglish (US)
Title of host publicationField-Programmable Logic and Applications
Subtitle of host publicationReconfigurable Computing is Going Mainstream - 12th International Conference, FPL 2002, Proceedings
PublisherSpringer Verlag
Number of pages10
ISBN (Print)3540441085, 9783540441083
StatePublished - 2002

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2438 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science


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