Abstract
Continuous reduction of feature dimensions in modern computer chips increases the challenge of measuring them. The state-of-the-art technology for imaging and fault isolation in integrated circuits (ICs) is done from the backside and uses a solid immersion lens (SIL) that sits directly on the back of the substrate to be imaged. A SIL can drastically increase the Numerical Aperture (NA) of the system and values of 3.5 are possible in silicon ICs. The physical placement of the lens requires high precision and good optical contact with no more than a 5nm gap under any portion of the lens. Commercial failure analysis systems require integration of the SIL with an objective system. This paper discusses the design of an integrated objective for imaging with an aplanatic SIL (aSIL).
Original language | English (US) |
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Title of host publication | Proceedings - ASPE 2012 Summer Topical Meeting |
Subtitle of host publication | Precision Engineering and Mechatronics Supporting the Semiconductor Industry |
Pages | 105-108 |
Number of pages | 4 |
Volume | 53 |
State | Published - Dec 1 2012 |
Event | ASPE 2012 Summer Topical Meeting on Precision Engineering and Mechatronics Suporting the Semiconductor Industry - Berkeley, CA, United States Duration: Jun 24 2012 → Jun 26 2012 |
Other
Other | ASPE 2012 Summer Topical Meeting on Precision Engineering and Mechatronics Suporting the Semiconductor Industry |
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Country/Territory | United States |
City | Berkeley, CA |
Period | 6/24/12 → 6/26/12 |
ASJC Scopus subject areas
- Engineering (miscellaneous)