@inproceedings{bddca1b3fe06447399cea939eff0766d,
title = "Floorplanning with graph attention",
abstract = "Floorplanning has long been a critical physical design task with high computation complexity. Its key objective is to determine the initial locations of macros and standard cells with optimized wirelength for a given area constraint. This paper presents Flora, a graph attention-based floorplanner to learn an optimized mapping between circuit connectivity and physical wirelength, and produce a chip floorplan using efficient model inference. Flora has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, Flora improves placement runtime by 18%, with 2% wirelength reduction on average.",
keywords = "deep learning, electronic design automation, floorplanning, graph attention network, physical design",
author = "Yiting Liu and Ziyi Ju and Zhengming Li and Mingzhi Dong and Hai Zhou and Jia Wang and Fan Yang and Xuan Zeng and Li Shang",
note = "Publisher Copyright: {\textcopyright} 2022 ACM.; 59th ACM/IEEE Design Automation Conference, DAC 2022 ; Conference date: 10-07-2022 Through 14-07-2022",
year = "2022",
month = jul,
day = "10",
doi = "10.1145/3489517.3530484",
language = "English (US)",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1303--1308",
booktitle = "Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022",
address = "United States",
}