FPGA implementation of a 64-bit BID-based decimal floating-point adder/subtractor

Amin Farmahini-Farahani*, Charles Tsen, Katherine Compton

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Demand for Decimal Floating-point (DFP) arithmetic is growing. Yet most processors do not include hardware DFP support, and must instead use slow software DFP libraries. FPGAs are a potential solution to add hardware-based high-performance, parallel DFP engines to existing compute clusters without completely replacing those systems. This paper describes the FPGA implementation of a 64-bit DFP adder using Binary Integer Decimal (BID) encoding. We present a variety of design tradeoffs possible for different modules of the DFP adder, and compare these for implementation on a Xilinx Virtex-5 FPGA. Choosing the best options, we improve the frequency of the DFP adder from the baseline hardware design's 68 MHz to over 163 MHz and decrease total latency by up to 2.4x. The optimized design requires only a small increase in resources. This is the first presentation of a BID-based DFP adder for FPGAs.

Original languageEnglish (US)
Title of host publicationProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09
Pages518-521
Number of pages4
DOIs
StatePublished - 2009
Externally publishedYes
Event2009 International Conference on Field-Programmable Technology, FPT'09 - Sydney, Australia
Duration: Dec 9 2009Dec 11 2009

Publication series

NameProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Other

Other2009 International Conference on Field-Programmable Technology, FPT'09
Country/TerritoryAustralia
CitySydney
Period12/9/0912/11/09

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Software

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