TY - JOUR
T1 - Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines
AU - Garikapati, Sasank
AU - Nagulu, Aravind
AU - Kadota, Igor
AU - Essawy, Mostafa
AU - Chen, Tingjun
AU - Wang, Shibo
AU - Pande, Tanvi
AU - Natarajan, Arun S.
AU - Zussman, Gil
AU - Krishnaswamy, Harish
N1 - Publisher Copyright:
© 1966-2012 IEEE.
PY - 2024/7/1
Y1 - 2024/7/1
N2 - The self-interference (SI) channels in full-duplex (FD) radios have large nano-second-scale delay spreads, which poses a significant challenge in designing SI cancelers that can emulate the SI channel over wide bandwidths. Passive implementations of high delay lines have a prohibitively large form factor and loss when implemented on silicon, whereas active implementations suffer from noise and linearity penalties. In this work, we leverage time-interleaved multi-path switched-capacitor (SC) circuits to provide large wideband delays with a small form factor and low power (LP) consumption to implement RF and baseband (BB) cancelers in an FD receiver (RX). We utilize capacitor stacking to obtain passive voltage gain to compensate for the loss of these delay elements, thus permitting an increased number of interleaved paths and, hence, a higher delay. Furthermore, to reduce the RX noise figure (NF) penalty due to injecting the cancellation signal into the receiver, we introduce a novel low-noise trans-impedance amplifier (LNTA) architecture, which injects the cancellation signal into RX and also accomplishes finite impulse response (FIR) filter weighting and summation. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 0.1 to 1 GHz. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging from 0 to 7.75 ns/0 to 85 ns while consuming 7.4- and 1.9-mW dc power per tap, respectively. These large tunable delays enable 41-/38-dB integrated SI cancellation for 40-/80-MHz bandwidth over 29-dB isolation provided by a CMOS circulator operating at 0.95 GHz. The canceler handles a transmitter (TX) power of up to +10/+15 dBm in LP/high-power (HP) modes with 0.8-/2.8-dB RX NF degradation.
AB - The self-interference (SI) channels in full-duplex (FD) radios have large nano-second-scale delay spreads, which poses a significant challenge in designing SI cancelers that can emulate the SI channel over wide bandwidths. Passive implementations of high delay lines have a prohibitively large form factor and loss when implemented on silicon, whereas active implementations suffer from noise and linearity penalties. In this work, we leverage time-interleaved multi-path switched-capacitor (SC) circuits to provide large wideband delays with a small form factor and low power (LP) consumption to implement RF and baseband (BB) cancelers in an FD receiver (RX). We utilize capacitor stacking to obtain passive voltage gain to compensate for the loss of these delay elements, thus permitting an increased number of interleaved paths and, hence, a higher delay. Furthermore, to reduce the RX noise figure (NF) penalty due to injecting the cancellation signal into the receiver, we introduce a novel low-noise trans-impedance amplifier (LNTA) architecture, which injects the cancellation signal into RX and also accomplishes finite impulse response (FIR) filter weighting and summation. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 0.1 to 1 GHz. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging from 0 to 7.75 ns/0 to 85 ns while consuming 7.4- and 1.9-mW dc power per tap, respectively. These large tunable delays enable 41-/38-dB integrated SI cancellation for 40-/80-MHz bandwidth over 29-dB isolation provided by a CMOS circulator operating at 0.95 GHz. The canceler handles a transmitter (TX) power of up to +10/+15 dBm in LP/high-power (HP) modes with 0.8-/2.8-dB RX NF degradation.
KW - Capacitor stacking
KW - delay lines
KW - full duplex (FD)
KW - multipath switched capacitors (SCs)
KW - self-interference (SI)
KW - time-domain equalization (TDE)
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UR - http://www.scopus.com/inward/citedby.url?scp=85192217321&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2024.3351615
DO - 10.1109/JSSC.2024.3351615
M3 - Article
AN - SCOPUS:85192217321
SN - 0018-9200
VL - 59
SP - 2105
EP - 2120
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 7
ER -