Gate sizing for crosstalk reduction under timing constraints by Lagrangian Relaxation

Debjit Sinha*, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

17 Scopus citations

Abstract

This paper presents a post-route, timing-constrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce crosstalk in deep sub-micron VLSI circuits. It is however critical to ensure that the timing constraints of the circuit are not violated after sizing. We present an iterative gate-sizing algorithm for crosstalk reduction based on Lagrangian Relaxation that optimizes area and power while ensuring that the given timing constraints are met. Experimental results demonstrating the effectiveness of the algorithm are reported for the ISCAS benchmarks and other large circuits with comparisons to an alternative design methodology.

Original languageEnglish (US)
Article number1A.3
Pages (from-to)14-19
Number of pages6
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
StatePublished - Dec 1 2004
EventICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 7 2004Nov 11 2004

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Fingerprint

Dive into the research topics of 'Gate sizing for crosstalk reduction under timing constraints by Lagrangian Relaxation'. Together they form a unique fingerprint.

Cite this