TY - GEN
T1 - Generation of control and data flow graphs from scheduled and pipelined assembly code
AU - Zaretsky, David C.
AU - Mittal, Gaurav
AU - Dick, Robert
AU - Banerjee, Prith
PY - 2006
Y1 - 2006
N2 - High-level synthesis tools generally convert abstract designs described in a high-level language into a control and data flow graph (CDFG), which is then optimized and mapped to hardware. However, there has been little work on generating CDFGs from highly pipelined software binaries, which complicate the problem of determining data flow propagation and dependencies. This paper presents a methodology for generating CDFGs from highly pipelined and scheduled assembly code that correctly represents the data dependencies and propagation of data through the program control flow. This process consists of three stages: generating a control flow graph, linearizing the assembly code, and generating the data flow graph. The proposed methodology was implemented in the FREEDOM compiler and tested on 8 highly pipelined software binaries. Results indicate that data dependencies were correctly identified in the designs, allowing the compiler to perform complex optimizations to reduce clock cycles.
AB - High-level synthesis tools generally convert abstract designs described in a high-level language into a control and data flow graph (CDFG), which is then optimized and mapped to hardware. However, there has been little work on generating CDFGs from highly pipelined software binaries, which complicate the problem of determining data flow propagation and dependencies. This paper presents a methodology for generating CDFGs from highly pipelined and scheduled assembly code that correctly represents the data dependencies and propagation of data through the program control flow. This process consists of three stages: generating a control flow graph, linearizing the assembly code, and generating the data flow graph. The proposed methodology was implemented in the FREEDOM compiler and tested on 8 highly pipelined software binaries. Results indicate that data dependencies were correctly identified in the designs, allowing the compiler to perform complex optimizations to reduce clock cycles.
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U2 - 10.1007/978-3-540-69330-7_6
DO - 10.1007/978-3-540-69330-7_6
M3 - Conference contribution
AN - SCOPUS:43949108561
SN - 3540693297
SN - 9783540693291
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 76
EP - 90
BT - Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers
T2 - 18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005
Y2 - 20 October 2005 through 22 October 2005
ER -