Global resource sharing for synthesis of control data flow graphs on FPGAs

Seda Ogrenci Memik*, Gokhan Memik, Roozbeh Jafari, Eren Kursun

*Corresponding author for this work

Research output: Contribution to journalConference article

21 Scopus citations

Abstract

In this paper we discuss the global resource sharing problem during synthesis of control data flow graphs for FPGAs. We first define the Global Resource Sharing (GRS) problem. Then, we introduce the Global Inter Basic Block Resource Sharing (GIBBS) technique to solve the GRS problem. We developed five heuristics to solve the GRS problem. The first tries to minimize the number of connections between modules, the second considers the area gain, the third uses the criticality of operations assigned to resources as a measure for deciding on merging any given pair of resources, the fourth tries to capture common resource chains and overlap those to minimize both area and delay, and the fifth is the combination of these heuristics. While applying resource sharing, we also consider the execution frequency of the basic blocks. Using our techniques we synthesized several CDFGs representing applications from MediaBench suite. Our results show that, we can reduce the total area requirement by 44% on average (up to 59%) while increasing the execution time by 6% on average.

Original languageEnglish (US)
Pages (from-to)604-609
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
StatePublished - Jan 1 2003
EventProceedings of the 40th Design Automation Conference - Anaheim, CA, United States
Duration: Jun 2 2003Jun 6 2003

Keywords

  • Control Data Flow Graph
  • FPGA
  • Resource Sharing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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