TY - JOUR
T1 - Graphene-enabled and directed nanomaterial placement from solution for large-scale device integration
AU - Engel, Michael
AU - Farmer, Damon B.
AU - Azpiroz, Jaione Tirapu
AU - Seo, Jung Woo T.
AU - Kang, Joohoon
AU - Avouris, Phaedon
AU - Hersam, Mark C.
AU - Krupke, Ralph
AU - Steiner, Mathias
N1 - Funding Information:
We thank Christos Dimitrakopoulos (University of Massachusetts, Amherst, Massachusetts, USA) for supplying graphene on SiC, Bruce Ek and Jim Bucchignano (both IBM Research) for expert technical assistance, and Ulisses Mello (IBM Research) for support. J.K., J.-W.T.S., and M.C.H acknowledge the support from the National Science Foundation (DMR-1505849) for the preparation of nanomaterial dispersions.
Publisher Copyright:
© 2018, The Author(s).
PY - 2018/12/1
Y1 - 2018/12/1
N2 - Directed placement of solution-based nanomaterials at predefined locations with nanoscale precision limits bottom-up integration in semiconductor process technology. We report a method for electric-field-assisted placement of nanomaterials from solution by means of large-scale graphene layers featuring nanoscale deposition sites. The structured graphene layers are prepared via either transfer or synthesis on standard substrates, and then are removed once nanomaterial deposition is completed, yielding material assemblies with nanoscale resolution that cover surface areas >1 mm2. In order to demonstrate the broad applicability, we have assembled representative zero-dimensional, one-dimensional, and two-dimensional semiconductors at predefined substrate locations and integrated them into nanoelectronic devices. Ultimately, this method opens a route to bottom-up integration of nanomaterials for industry-scale applications.
AB - Directed placement of solution-based nanomaterials at predefined locations with nanoscale precision limits bottom-up integration in semiconductor process technology. We report a method for electric-field-assisted placement of nanomaterials from solution by means of large-scale graphene layers featuring nanoscale deposition sites. The structured graphene layers are prepared via either transfer or synthesis on standard substrates, and then are removed once nanomaterial deposition is completed, yielding material assemblies with nanoscale resolution that cover surface areas >1 mm2. In order to demonstrate the broad applicability, we have assembled representative zero-dimensional, one-dimensional, and two-dimensional semiconductors at predefined substrate locations and integrated them into nanoelectronic devices. Ultimately, this method opens a route to bottom-up integration of nanomaterials for industry-scale applications.
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U2 - 10.1038/s41467-018-06604-4
DO - 10.1038/s41467-018-06604-4
M3 - Article
C2 - 30291247
AN - SCOPUS:85054428402
SN - 2041-1723
VL - 9
JO - Nature Communications
JF - Nature Communications
IS - 1
M1 - 4095
ER -