Abstract
In this paper, a novel Greybox design methodology is proposed to establish a design and co-optimization flow across the boundary of conventional software and hardware design. The dynamic timing of each software instruction is simulated and associated with processor hardware design, which provides the basis of ultra-dynamic clock management. The proposed scheme effectively implements the instruction-based clock management and achieves 21.71% frequency speedup. Besides, a novel program-driven hardware optimization flow is proposed, in which software operations are mapped with hardware gate netlist and sorted by the usage frequency. The experiments on an ARM based pipeline design in commercial 65nm CMOS process show an extra 10% frequency speedup is obtained with high optimization efficiency. Overall, the proposed Greybox design method achieves frequency speedup by 31.56%, comparing with conventional design method.
Original language | English (US) |
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Title of host publication | Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781450349277 |
DOIs | |
State | Published - Jun 18 2017 |
Event | 54th Annual Design Automation Conference, DAC 2017 - Austin, United States Duration: Jun 18 2017 → Jun 22 2017 |
Publication series
Name | Proceedings - Design Automation Conference |
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Volume | Part 128280 |
ISSN (Print) | 0738-100X |
Other
Other | 54th Annual Design Automation Conference, DAC 2017 |
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Country/Territory | United States |
City | Austin |
Period | 6/18/17 → 6/22/17 |
Funding
This work is partially supported by NSF grants CCF-1618065 and CCF-1116610.
ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation