## Abstract

Decimal floating-point (DFP) arithmetic is becoming increasingly important and specifications for it are included in the revised IEEE 754 standard for floating-point arithmetic (IEEE 754-2008). The binary encoding of DFP numbers specified in IEEE 754-2008 is commonly referred to as Binary-Integer Decimal (BID). BID uses a binary integer to encode the significant, which allows it to leverage existing high-speed binary circuits. However, performing decimal rounding on these binary significant is challenging. In this paper, we propose and evaluate several approaches to perform decimal rounding in hardware for DFP numbers that use the BID encoding. We summarize several rounding techniques, present the theory and design of each proposed rounding unit, and use synthesis results to evaluate the critical path delay, latency, and area of rounding units for 64-bit BID numbers. Our results indicate that the bulk of each rounder design is occupied by a binary fixed-point multiplier that can be shared with other integer and floating-point operations. This is the first paper to present and compare a variety of techniques for BID-based rounding hardware. These techniques are valuable to designers of BID-based DFP solutions.

Original language | English (US) |
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Article number | 5669290 |

Pages (from-to) | 614-627 |

Number of pages | 14 |

Journal | IEEE Transactions on Computers |

Volume | 60 |

Issue number | 5 |

DOIs | |

State | Published - 2011 |

Externally published | Yes |

## Keywords

- Arithmetic algorithms
- binary-integer decimal
- computer arithmetic
- decimal floating point
- hardware designs
- IEEE 754-2008
- rounding

## ASJC Scopus subject areas

- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics