Hardware requirements for neural-net optical character recognition

L. D. Jackel*, B. Boser, J. S. Denker, H. P. Graf, Y. Le Cun, I. Guyon, D. Henderson, R. E. Howard, W. Hubbard, S. A. Solla

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


Hardware architectures for character recognition are discussed, and choices for possible circuits are outlined. An advanced (and working) reconfigurable neural-net chip that mixes analog and digital processing is described. It is found that different approaches to image recognition often lead to neural-net architectures that have limited connectivity and repeated use of the same set of weights. This architecture is ideal for time-multiplexing (a combined parallel-series processing) on hardware systems that would be too small to evaluate the entire network in parallel. To make this process efficient, a chip needs to have shift registers to format the input data and additional registers to store intermediate results. Within this framework, it is possible to design chips that have broad utility, large connection capacity, and high speed. This was demonstrated by a new chip with 32,000 reconfigurable connections.

Original languageEnglish (US)
Title of host publicationIJCNN. International Joint Conference on Neural Networks
PublisherPubl by IEEE
Number of pages7
StatePublished - Dec 1 1990
Event1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3) - San Diego, CA, USA
Duration: Jun 17 1990Jun 21 1990


Other1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3)
CitySan Diego, CA, USA

ASJC Scopus subject areas

  • Engineering(all)


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