Hardware/software techniques for DRAM thermal management

Song Liu*, Brian Leung, Alexander Neckar, Seda Ogrenci Memik, Gokhan Memik, Nikos Hardavellas

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

31 Citations (Scopus)

Abstract

The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory modules. However, these approaches increase power consumption and operating temperatures: temperatures in existing DRAM modules can rise to over 95°C. Another important property of DRAM temperature is the large variation in DRAM chip temperatures. In this paper, we present our analysis collected from measurements on a real system indicating that temperatures across DRAM chips can vary by over 10°C. This work aims to minimize this variation as well as the peak DRAM temperature. We first develop a thermal model to estimate the temperature of DRAM chips and validate this model against real temperature measurements. We then propose three hardware and software schemes to reduce peak temperatures. The first technique introduces a new cache line replacement policy that reduces the number of accesses to the overheating DRAM chips. The second technique utilizes a Memory Write Buffer to improve the access efficiency of the overheated chips. The third scheme intelligently allocates pages to relatively cooler ranks of the DIMM. Our experiments show that in a high performance memory system, our schemes reduce the peak DRAM chip temperature by as much as 8.39°C over 10 workloads (5.36°C on average). Our schemes also improve performance mainly due to reduction in thermal emergencies: for a baseline system with memory bandwidth throttling scheme, the IPC is improved by as much as 15.8% (4.1% on average).

Original languageEnglish (US)
Title of host publicationProceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Pages515-525
Number of pages11
DOIs
StatePublished - May 17 2011
Event17th International Symposium on High-Performance Computer Architecture, HPCA 2011 - San Antonio, TX, United States
Duration: Feb 12 2011Feb 16 2011

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other17th International Symposium on High-Performance Computer Architecture, HPCA 2011
CountryUnited States
CitySan Antonio, TX
Period2/12/112/16/11

Fingerprint

Dynamic random access storage
Temperature control
Hardware
Data storage equipment
Temperature
Temperature measurement
Electric power utilization
Bandwidth

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Liu, S., Leung, B., Neckar, A., Memik, S. O., Memik, G., & Hardavellas, N. (2011). Hardware/software techniques for DRAM thermal management. In Proceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011 (pp. 515-525). [5749756] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2011.5749756
Liu, Song ; Leung, Brian ; Neckar, Alexander ; Memik, Seda Ogrenci ; Memik, Gokhan ; Hardavellas, Nikos. / Hardware/software techniques for DRAM thermal management. Proceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011. 2011. pp. 515-525 (Proceedings - International Symposium on High-Performance Computer Architecture).
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title = "Hardware/software techniques for DRAM thermal management",
abstract = "The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory modules. However, these approaches increase power consumption and operating temperatures: temperatures in existing DRAM modules can rise to over 95°C. Another important property of DRAM temperature is the large variation in DRAM chip temperatures. In this paper, we present our analysis collected from measurements on a real system indicating that temperatures across DRAM chips can vary by over 10°C. This work aims to minimize this variation as well as the peak DRAM temperature. We first develop a thermal model to estimate the temperature of DRAM chips and validate this model against real temperature measurements. We then propose three hardware and software schemes to reduce peak temperatures. The first technique introduces a new cache line replacement policy that reduces the number of accesses to the overheating DRAM chips. The second technique utilizes a Memory Write Buffer to improve the access efficiency of the overheated chips. The third scheme intelligently allocates pages to relatively cooler ranks of the DIMM. Our experiments show that in a high performance memory system, our schemes reduce the peak DRAM chip temperature by as much as 8.39°C over 10 workloads (5.36°C on average). Our schemes also improve performance mainly due to reduction in thermal emergencies: for a baseline system with memory bandwidth throttling scheme, the IPC is improved by as much as 15.8{\%} (4.1{\%} on average).",
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Liu, S, Leung, B, Neckar, A, Memik, SO, Memik, G & Hardavellas, N 2011, Hardware/software techniques for DRAM thermal management. in Proceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011., 5749756, Proceedings - International Symposium on High-Performance Computer Architecture, pp. 515-525, 17th International Symposium on High-Performance Computer Architecture, HPCA 2011, San Antonio, TX, United States, 2/12/11. https://doi.org/10.1109/HPCA.2011.5749756

Hardware/software techniques for DRAM thermal management. / Liu, Song; Leung, Brian; Neckar, Alexander; Memik, Seda Ogrenci; Memik, Gokhan; Hardavellas, Nikos.

Proceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011. 2011. p. 515-525 5749756 (Proceedings - International Symposium on High-Performance Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory modules. However, these approaches increase power consumption and operating temperatures: temperatures in existing DRAM modules can rise to over 95°C. Another important property of DRAM temperature is the large variation in DRAM chip temperatures. In this paper, we present our analysis collected from measurements on a real system indicating that temperatures across DRAM chips can vary by over 10°C. This work aims to minimize this variation as well as the peak DRAM temperature. We first develop a thermal model to estimate the temperature of DRAM chips and validate this model against real temperature measurements. We then propose three hardware and software schemes to reduce peak temperatures. The first technique introduces a new cache line replacement policy that reduces the number of accesses to the overheating DRAM chips. The second technique utilizes a Memory Write Buffer to improve the access efficiency of the overheated chips. The third scheme intelligently allocates pages to relatively cooler ranks of the DIMM. Our experiments show that in a high performance memory system, our schemes reduce the peak DRAM chip temperature by as much as 8.39°C over 10 workloads (5.36°C on average). Our schemes also improve performance mainly due to reduction in thermal emergencies: for a baseline system with memory bandwidth throttling scheme, the IPC is improved by as much as 15.8% (4.1% on average).

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Liu S, Leung B, Neckar A, Memik SO, Memik G, Hardavellas N. Hardware/software techniques for DRAM thermal management. In Proceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011. 2011. p. 515-525. 5749756. (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2011.5749756