HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs

Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu Yeon Wei, David Brooks

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Scopus citations

Abstract

Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.

Original languageEnglish (US)
Title of host publication41st Annual International Symposium on Computer Architecture, ISCA 2014 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages217-228
Number of pages12
ISBN (Print)9781479943968
DOIs
StatePublished - 2014
Event2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014 - Minneapolis, MN, United States
Duration: Jun 14 2014Jun 18 2014

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014
CountryUnited States
CityMinneapolis, MN
Period6/14/146/18/14

ASJC Scopus subject areas

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs'. Together they form a unique fingerprint.

Cite this