High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification with Pipelined Mixed-Signal Time-Domain Computing

Zhengyu Chen*, Jie Gu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Time-series classification (TSC) is a challenging problem in machine learning and significant efforts have been made to improve its speed and computation efficiency. Among various approaches, dynamic time warping (DTW) algorithm is one of the most prevalent methods for TSC due to its succinctness and generality. To improve the throughput of the operation, this work presents a mixed-signal DTW accelerator utilizing mixed-signal time-domain (TD) computing where signals are encoded and processed using time pulses. A pipelined operation is enabled by a specially designed time flip-flop (TFF) circuit leading to dramatic improvements in performance and scalability of the operation. A 65-nm CMOS test chip was implemented and measured. The results show more than 9× improvements in throughput compared with prior work on TSC. As most existing TD designs suffer from the lack of TD storage elements, this work utilizes sequential circuit elements in TD computing extending the capability of time-based circuits.

Original languageEnglish (US)
Article number9199261
Pages (from-to)624-635
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume56
Issue number2
DOIs
StatePublished - Feb 2021

Keywords

  • Dynamic programming
  • dynamic time warping (DTW)
  • energy efficient computing
  • machine learning
  • mixed-signal time-domain (TD) computing (MSTC)
  • time flip-flop (TFF)
  • time-series classification (TSC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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