TY - JOUR
T1 - High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification with Pipelined Mixed-Signal Time-Domain Computing
AU - Chen, Zhengyu
AU - Gu, Jie
N1 - Funding Information:
Manuscript received March 18, 2020; revised July 23, 2020; accepted August 20, 2020. Date of publication September 17, 2020; date of current version January 28, 2021. This article was approved by Associate Editor Edith Beigne. This work was supported in part by the National Science Foundation under Grant CCF-1846424. (Corresponding author: Zhengyu Chen.) The authors are with the Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL 60208 USA (e-mail: zhengyuchen2015@u.northwestern.edu).
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2021/2
Y1 - 2021/2
N2 - Time-series classification (TSC) is a challenging problem in machine learning and significant efforts have been made to improve its speed and computation efficiency. Among various approaches, dynamic time warping (DTW) algorithm is one of the most prevalent methods for TSC due to its succinctness and generality. To improve the throughput of the operation, this work presents a mixed-signal DTW accelerator utilizing mixed-signal time-domain (TD) computing where signals are encoded and processed using time pulses. A pipelined operation is enabled by a specially designed time flip-flop (TFF) circuit leading to dramatic improvements in performance and scalability of the operation. A 65-nm CMOS test chip was implemented and measured. The results show more than 9× improvements in throughput compared with prior work on TSC. As most existing TD designs suffer from the lack of TD storage elements, this work utilizes sequential circuit elements in TD computing extending the capability of time-based circuits.
AB - Time-series classification (TSC) is a challenging problem in machine learning and significant efforts have been made to improve its speed and computation efficiency. Among various approaches, dynamic time warping (DTW) algorithm is one of the most prevalent methods for TSC due to its succinctness and generality. To improve the throughput of the operation, this work presents a mixed-signal DTW accelerator utilizing mixed-signal time-domain (TD) computing where signals are encoded and processed using time pulses. A pipelined operation is enabled by a specially designed time flip-flop (TFF) circuit leading to dramatic improvements in performance and scalability of the operation. A 65-nm CMOS test chip was implemented and measured. The results show more than 9× improvements in throughput compared with prior work on TSC. As most existing TD designs suffer from the lack of TD storage elements, this work utilizes sequential circuit elements in TD computing extending the capability of time-based circuits.
KW - Dynamic programming
KW - dynamic time warping (DTW)
KW - energy efficient computing
KW - machine learning
KW - mixed-signal time-domain (TD) computing (MSTC)
KW - time flip-flop (TFF)
KW - time-series classification (TSC)
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U2 - 10.1109/JSSC.2020.3021066
DO - 10.1109/JSSC.2020.3021066
M3 - Article
AN - SCOPUS:85100314802
SN - 0018-9200
VL - 56
SP - 624
EP - 635
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 2
M1 - 9199261
ER -