TY - GEN
T1 - Holistic Energy Management with μprocessor Co-Optimization in Fully Integrated Battery-Less IoTs
AU - Hester, Josiah David
AU - Jia, Tianyu
AU - Gu, Jie
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - Fully integrating on-chip power management modules and microprocessor into a system-on-a-chip (SoC) provides many benefits including lower cost and higher levels of optimization, especially for battery-less energy harvesting operation. However, previous studies have only focused on optimization of individual module, e.g. power converter. There is a lack of systematic optimization of energy efficiency considering microprocessor, regulator, and harvester. This paper performs a holistic study on power efficiency of the whole energy harvesting system including solar cells, on-chip voltage regulators and microprocessors. An optimal scheduling and operation strategy is proposed for achieving the best efficiency and system level performance while avoiding local minimum as in conventional approach. We show that the minimum energy point is different from conventional approaches without a holistic view of the system. We demonstrated the study and proposed scheme using a battery-less solar energy harvesting system and a 65nm fully integrated test chip with 20% additional energy savings.
AB - Fully integrating on-chip power management modules and microprocessor into a system-on-a-chip (SoC) provides many benefits including lower cost and higher levels of optimization, especially for battery-less energy harvesting operation. However, previous studies have only focused on optimization of individual module, e.g. power converter. There is a lack of systematic optimization of energy efficiency considering microprocessor, regulator, and harvester. This paper performs a holistic study on power efficiency of the whole energy harvesting system including solar cells, on-chip voltage regulators and microprocessors. An optimal scheduling and operation strategy is proposed for achieving the best efficiency and system level performance while avoiding local minimum as in conventional approach. We show that the minimum energy point is different from conventional approaches without a holistic view of the system. We demonstrated the study and proposed scheme using a battery-less solar energy harvesting system and a 65nm fully integrated test chip with 20% additional energy savings.
KW - Low-power design
KW - Multi-domain power/energy management
KW - Power/energy/thermal aware architecture design
UR - http://www.scopus.com/inward/record.url?scp=85062227037&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85062227037&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2018.8618523
DO - 10.1109/SOCC.2018.8618523
M3 - Conference contribution
AN - SCOPUS:85062227037
T3 - International System on Chip Conference
SP - 61
EP - 66
BT - Proceedings - 31st IEEE International System on Chip Conference, SOCC 2018
A2 - Stan, Mircea
A2 - Bhatia, Karan
A2 - Li, Helen
A2 - Alioto, Massimo
A2 - Sridhar, Ramalingam
PB - IEEE Computer Society
T2 - 31st IEEE International System on Chip Conference, SOCC 2018
Y2 - 4 September 2018 through 7 September 2018
ER -
