Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing

Shaodi Wang; Saptadeep Pal; Tianmu Li; Andrew Pan; Cecile Grezes; Pedram Khalili-Amiri; Kang L. Wang; Puneet Gupta

doi:10.23919/DATE.2017.7927218

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing

Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili-Amiri, Kang L. Wang, Puneet Gupta

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machine-learning algorithm). 3X-37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs.

Original language	English (US)
Title of host publication	Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1438-1443
Number of pages	6
ISBN (Electronic)	9783981537093
DOIs	https://doi.org/10.23919/DATE.2017.7927218
State	Published - May 11 2017
Event	20th Design, Automation and Test in Europe, DATE 2017 - Swisstech, Lausanne, Switzerland Duration: Mar 27 2017 → Mar 31 2017

Publication series

Name	Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017

Other

Other	20th Design, Automation and Test in Europe, DATE 2017
Country	Switzerland
City	Swisstech, Lausanne
Period	3/27/17 → 3/31/17

Keywords

Negative differential resistance
Non-volatile
Stochastic computing
Voltage-controlled magnetic tunnel junction

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Safety, Risk, Reliability and Quality

Access to Document

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Wang, S., Pal, S., Li, T., Pan, A., Grezes, C., Khalili-Amiri, P., Wang, K. L., & Gupta, P. (2017). Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017 (pp. 1438-1443). [7927218] (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE.2017.7927218

Wang, Shaodi ; Pal, Saptadeep ; Li, Tianmu ; Pan, Andrew ; Grezes, Cecile ; Khalili-Amiri, Pedram ; Wang, Kang L. ; Gupta, Puneet. / Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1438-1443 (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017).

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title = "Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing",

abstract = "In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machine-learning algorithm). 3X-37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs.",

keywords = "Negative differential resistance, Non-volatile, Stochastic computing, Voltage-controlled magnetic tunnel junction",

author = "Shaodi Wang and Saptadeep Pal and Tianmu Li and Andrew Pan and Cecile Grezes and Pedram Khalili-Amiri and Wang, {Kang L.} and Puneet Gupta",

year = "2017",

month = may,

day = "11",

doi = "10.23919/DATE.2017.7927218",

language = "English (US)",

series = "Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017",

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pages = "1438--1443",

booktitle = "Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017",

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note = "20th Design, Automation and Test in Europe, DATE 2017 ; Conference date: 27-03-2017 Through 31-03-2017",

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Wang, S, Pal, S, Li, T, Pan, A, Grezes, C, Khalili-Amiri, P, Wang, KL & Gupta, P 2017, Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. in Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017., 7927218, Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers Inc., pp. 1438-1443, 20th Design, Automation and Test in Europe, DATE 2017, Swisstech, Lausanne, Switzerland, 3/27/17. https://doi.org/10.23919/DATE.2017.7927218

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. / Wang, Shaodi; Pal, Saptadeep; Li, Tianmu; Pan, Andrew; Grezes, Cecile; Khalili-Amiri, Pedram; Wang, Kang L.; Gupta, Puneet.

Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1438-1443 7927218 (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Wang, Shaodi

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AB - In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machine-learning algorithm). 3X-37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs.

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Wang S, Pal S, Li T, Pan A, Grezes C, Khalili-Amiri P et al. Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1438-1443. 7927218. (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017). https://doi.org/10.23919/DATE.2017.7927218

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing

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Keywords

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