TY - GEN
T1 - Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing
AU - Wang, Shaodi
AU - Pal, Saptadeep
AU - Li, Tianmu
AU - Pan, Andrew
AU - Grezes, Cecile
AU - Khalili-Amiri, Pedram
AU - Wang, Kang L.
AU - Gupta, Puneet
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/5/11
Y1 - 2017/5/11
N2 - In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machine-learning algorithm). 3X-37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs.
AB - In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machine-learning algorithm). 3X-37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs.
KW - Negative differential resistance
KW - Non-volatile
KW - Stochastic computing
KW - Voltage-controlled magnetic tunnel junction
UR - http://www.scopus.com/inward/record.url?scp=85020180380&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85020180380&partnerID=8YFLogxK
U2 - 10.23919/DATE.2017.7927218
DO - 10.23919/DATE.2017.7927218
M3 - Conference contribution
AN - SCOPUS:85020180380
T3 - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
SP - 1438
EP - 1443
BT - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th Design, Automation and Test in Europe, DATE 2017
Y2 - 27 March 2017 through 31 March 2017
ER -