Identifying and predicting timing-critical instructions to boost timing speculation

Jing Xin*, Russell E Joseph

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

37 Scopus citations


Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins and eliminating power/performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. To a large extent existing work has relied on statistical error models and has not evaluated potential disparity of error rates at the level of static instructions. In this paper, we analyze gate-level hardware models for an execution pipeline and demonstrate pronounced locality in instruction-level error rates due to value locality and data dependences. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and error padding techniques to avoid the full recovery cost of timing errors. We show that with simple prediction strategies our mechanism can reduce 80% of the performance penalty incurred by error recovery on average. This allows us to alleviate some limitations of timing speculation and improves energy-efficiency by 21% when compared to baseline timing speculation techniques using the same dynamic adaptive tuning mechanism.

Original languageEnglish (US)
Title of host publicationMICRO 44 - Proceedings of the 44th Annual IEEE/ACM Symposium on Microarchitecture
Number of pages12
StatePublished - Dec 1 2011
Event44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44 - Porto Alegre, RS, Brazil
Duration: Dec 4 2011Dec 7 2011

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451


Other44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44
CityPorto Alegre, RS


  • pipeline
  • power management
  • timing speculation

ASJC Scopus subject areas

  • Hardware and Architecture

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