Impact of interconnect protocols and device-level performance on distributed active storage architectures

Steve C. Chiu, Alok Nidhi Choudhary

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Distributed active storage architectures are designed to offload user-level processing to the peripheral from the host servers. In this paper, the author reports preliminary investigation on performance and fault recovery designs, as impacted by emerging storage interconnect protocols and novel state-of-the-art storage devices. Empirical results obtained using validated device-level and interconnect data demonstrate the significance of the said parameters on the overall system performance and reliability.

Original languageEnglish (US)
Title of host publicationProceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05
Pages393-400
Number of pages8
StatePublished - Dec 1 2005
Event2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05 - Las Vegas, NV, United States
Duration: Jun 27 2005Jun 30 2005

Publication series

NameProceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05
Volume1

Other

Other2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05
CountryUnited States
CityLas Vegas, NV
Period6/27/056/30/05

Keywords

  • Distributed Storage
  • InfiniBand
  • MEMS
  • Parallel I/O modeling
  • Performance analysis

ASJC Scopus subject areas

  • Computer Science Applications
  • Information Systems

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