Impact of interconnect protocols and device-level performance on distributed active storage architectures

Steve C. Chiu; Alok Nidhi Choudhary

Impact of interconnect protocols and device-level performance on distributed active storage architectures

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Distributed active storage architectures are designed to offload user-level processing to the peripheral from the host servers. In this paper, the author reports preliminary investigation on performance and fault recovery designs, as impacted by emerging storage interconnect protocols and novel state-of-the-art storage devices. Empirical results obtained using validated device-level and interconnect data demonstrate the significance of the said parameters on the overall system performance and reliability.

Original language	English (US)
Title of host publication	Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05
Pages	393-400
Number of pages	8
State	Published - Dec 1 2005
Event	2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05 - Las Vegas, NV, United States Duration: Jun 27 2005 → Jun 30 2005

Publication series

Name	Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05
Volume	1

Other

Other	2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05
Country/Territory	United States
City	Las Vegas, NV
Period	6/27/05 → 6/30/05

Keywords

Distributed Storage
InfiniBand
MEMS
Parallel I/O modeling
Performance analysis

ASJC Scopus subject areas

Computer Science Applications
Information Systems

Cite this

Chiu, S. C., & Choudhary, A. N. (2005). Impact of interconnect protocols and device-level performance on distributed active storage architectures. In Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05 (pp. 393-400). (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; Vol. 1).

Chiu, Steve C. ; Choudhary, Alok Nidhi. / Impact of interconnect protocols and device-level performance on distributed active storage architectures. Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. 2005. pp. 393-400 (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05).

@inproceedings{c5d330b29ca449adade84878517507b4,

title = "Impact of interconnect protocols and device-level performance on distributed active storage architectures",

abstract = "Distributed active storage architectures are designed to offload user-level processing to the peripheral from the host servers. In this paper, the author reports preliminary investigation on performance and fault recovery designs, as impacted by emerging storage interconnect protocols and novel state-of-the-art storage devices. Empirical results obtained using validated device-level and interconnect data demonstrate the significance of the said parameters on the overall system performance and reliability.",

keywords = "Distributed Storage, InfiniBand, MEMS, Parallel I/O modeling, Performance analysis",

author = "Chiu, {Steve C.} and Choudhary, {Alok Nidhi}",

year = "2005",

month = dec,

day = "1",

language = "English (US)",

isbn = "9781932415582",

series = "Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05",

pages = "393--400",

booktitle = "Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05",

note = "2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05 ; Conference date: 27-06-2005 Through 30-06-2005",

}

Chiu, SC & Choudhary, AN 2005, Impact of interconnect protocols and device-level performance on distributed active storage architectures. in Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05, vol. 1, pp. 393-400, 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05, Las Vegas, NV, United States, 6/27/05.

Impact of interconnect protocols and device-level performance on distributed active storage architectures. / Chiu, Steve C.; Choudhary, Alok Nidhi.

Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. 2005. p. 393-400 (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Impact of interconnect protocols and device-level performance on distributed active storage architectures

AU - Chiu, Steve C.

AU - Choudhary, Alok Nidhi

PY - 2005/12/1

Y1 - 2005/12/1

N2 - Distributed active storage architectures are designed to offload user-level processing to the peripheral from the host servers. In this paper, the author reports preliminary investigation on performance and fault recovery designs, as impacted by emerging storage interconnect protocols and novel state-of-the-art storage devices. Empirical results obtained using validated device-level and interconnect data demonstrate the significance of the said parameters on the overall system performance and reliability.

AB - Distributed active storage architectures are designed to offload user-level processing to the peripheral from the host servers. In this paper, the author reports preliminary investigation on performance and fault recovery designs, as impacted by emerging storage interconnect protocols and novel state-of-the-art storage devices. Empirical results obtained using validated device-level and interconnect data demonstrate the significance of the said parameters on the overall system performance and reliability.

KW - Distributed Storage

KW - InfiniBand

KW - MEMS

KW - Parallel I/O modeling

KW - Performance analysis

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M3 - Conference contribution

AN - SCOPUS:63049127107

SN - 9781932415582

T3 - Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05

SP - 393

EP - 400

BT - Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05

T2 - 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05

Y2 - 27 June 2005 through 30 June 2005

ER -

Chiu SC, Choudhary AN. Impact of interconnect protocols and device-level performance on distributed active storage architectures. In Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. 2005. p. 393-400. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05).

Impact of interconnect protocols and device-level performance on distributed active storage architectures

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

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