Impact of modern process technologies on the electrical parameters of interconnects

Debjit Sinha; Jianfeng Luo; Subramanian Rajagopalan; Shabbir Batterywala; Narendra V. Shenoy; Hai Zhou

doi:10.1109/VLSID.2007.90

Impact of modern process technologies on the electrical parameters of interconnects

Debjit Sinha^*, Jianfeng Luo, Subramanian Rajagopalan, Shabbir Batterywala, Narendra V. Shenoy, Hai Zhou

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant.

Original language	English (US)
Title of host publication	Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Pages	875-880
Number of pages	6
DOIs	https://doi.org/10.1109/VLSID.2007.90
State	Published - Dec 1 2007
Event	20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India Duration: Jan 6 2007 → Jan 10 2007

Other

Other	20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
Country	India
City	Bangalore
Period	1/6/07 → 1/10/07

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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title = "Impact of modern process technologies on the electrical parameters of interconnects",

abstract = "This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant.",

author = "Debjit Sinha and Jianfeng Luo and Subramanian Rajagopalan and Shabbir Batterywala and Shenoy, {Narendra V.} and Hai Zhou",

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booktitle = "Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems",

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Sinha, D, Luo, J, Rajagopalan, S, Batterywala, S, Shenoy, NV & Zhou, H 2007, Impact of modern process technologies on the electrical parameters of interconnects. in Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems., 4092151, pp. 875-880, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07, Bangalore, India, 1/6/07. https://doi.org/10.1109/VLSID.2007.90

Impact of modern process technologies on the electrical parameters of interconnects. / Sinha, Debjit; Luo, Jianfeng; Rajagopalan, Subramanian; Batterywala, Shabbir; Shenoy, Narendra V.; Zhou, Hai.

Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems. 2007. p. 875-880 4092151.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant.

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