Impact of modern process technologies on the electrical parameters of interconnects

Debjit Sinha*, Jianfeng Luo, Subramanian Rajagopalan, Shabbir Batterywala, Narendra V. Shenoy, Hai Zhou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant.

Original languageEnglish (US)
Title of host publicationProceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Pages875-880
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India
Duration: Jan 6 2007Jan 10 2007

Other

Other20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
CountryIndia
CityBangalore
Period1/6/071/10/07

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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