Abstract
This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant.
Original language | English (US) |
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Title of host publication | Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems |
Pages | 875-880 |
Number of pages | 6 |
DOIs | |
State | Published - Dec 1 2007 |
Event | 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India Duration: Jan 6 2007 → Jan 10 2007 |
Other
Other | 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 |
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Country | India |
City | Bangalore |
Period | 1/6/07 → 1/10/07 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering