Improving floating-point performance in less area: Fractured floating point units (FFPUs)

Neil Hockert, Katherine Compton*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Embedded systems designers often use fixed-point instead of floating-point due to the performance and area overhead of floating-point units. If the range of floating-point representation is required, the system may use a software-based floating-point library on an integer-only processor to save area-at the cost of much lower performance. Instead, we propose a Fractured Floating Point Unit (FFPU)-a hybrid solution that uses a set of custom hardware instructions to accelerate software-based floating-point emulation. An FFPU is intended as a compromise between software libraries and full FPUs in terms of both area and performance. We present four potential 32-bit FFPU designs for a Nios II soft processor. We compare their performance and area to the baseline Nios II, as well as a Nios II with a complete FPU. We show that an FFPU can improve various floating-point operations, including improving addition and subtraction performance by 24 to 52 percent over the baseline. This performance comes at a resource cost of only an 11 to 29 percent ALM increase, and no increase in DSP blocks.

Original languageEnglish (US)
Pages (from-to)31-46
Number of pages16
JournalJournal of Signal Processing Systems
Volume67
Issue number1
DOIs
StatePublished - Apr 2012
Externally publishedYes

Keywords

  • Acceleration
  • FFPU
  • Floating-point
  • FPGA
  • FPU

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modeling and Simulation
  • Hardware and Architecture

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