Instruction generation for hybrid reconfigurable systems

R. Kastner*, A. Kaplan, S. Ogrenci Memik, E. Bozorgzadeh

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

147 Scopus citations

Abstract

Future computing systems need to balance flexibility, specialization, and performance in order to meet market demands and the computing power required by new applications. Instruction generation is a vital component for determining these trade-offs. In this work, we present theory and an algorithm for instruction generation. The algorithm profiles a dataflow graph and iteratively contracts edges to create the templates. We discuss how to target the algorithm toward the novel problem of instruction generation for hybrid reconfigurable systems. In particular, we target the Strategically Programmable System, which embeds complex computational units such as ALUs, IP blocks, and so on into a configurable fabric. We argue that an essential compilation step for these systems is instruction generation, as it is needed to specify the functionality of the embedded computational units. In addition, instruction generation can be used to create soft reconfigurable macros-tightly sequenced prespecified operations placed in the reconfigurable fabric.

Original languageEnglish (US)
Pages (from-to)605-627
Number of pages23
JournalACM Transactions on Design Automation of Electronic Systems
Volume7
Issue number4
DOIs
StatePublished - Oct 2002

Keywords

  • FPGA
  • High-level synthesis
  • Reconfigurable computing

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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