Integrated floorplanning and interconnect planning

Hung Ming Chen*, Hai Zhou, F. Y. Young, D. F. Wong, Hannah H. Yang, Naveed Sherwani

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

57 Scopus citations


The VLSI fabrication has entered the deep sub-micron era and communication between different components has significantly increased. Interconnect delay has become the dominant factor in total circuit delay. As a result, it is necessary to start interconnect planning as early as possible. In this paper, we propose a method to combine interconnect planning with floorplanning. Our approach is based on the Wong-Liu floorplanning algorithm. When the positions, orientations, and shapes of the cells are decided, the pin positions and routing of the interconnects are decided as well. We use a multi-stage simulated annealing approach in which different interconnect planning methods are used in different ranges of temperatures to reduce running time. A temperature adjustment scheme is designed to give smooth transitions between different stages of simulated annealing. Experimental results show that our approach performs well.

Original languageEnglish (US)
Pages (from-to)354-357
Number of pages4
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
StatePublished - 1999
EventProceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-99) - San Jose, CA, USA
Duration: Nov 7 1999Nov 11 1999

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design


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