Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures

Keyphrases

• Reconfigurable Systems 100%
• Physical Design 100%
• Scheduling Design 100%
• Reconfigurable Computing Architecture 100%
• Xilinx 66%
• System Designer 33%
• Synthetic Approaches 33%
• Application Development 33%
• Keep up 33%
• Debugging 33%
• Performance Expectations 33%
• High-level Synthesis 33%
• Design Phase 33%
• System Application 33%
• Clock Frequency 33%
• FPGA Technology 33%
• Reconfigurable Computing 33%
• Computing Machines 33%
• Data Flow Graph 33%
• Testing Cycle 33%
• Growing Performance 33%
• VHDL Code 33%
• Fast Compilation 33%
• Place-and-route 33%

Computer Science

• Computer Architecture 100%
• Physical Design 100%
• reconfigurable computing 100%
• Design Phase 20%
• Performance Expectation 20%
• Computer Hardware 20%
• Application System 20%
• Placement Information 20%
• Capacity Device 20%
• High Level Synthesis 20%
• System Designer 20%
• Application Development 20%
• Data Flow Graph 20%
• Clock Frequency 20%
• Field Programmable Gate Arrays 20%