Interconnect estimation without packing via ACG floorplans

Jia Wang; Hai Zhou

doi:10.1145/1120725.1120928

Interconnect estimation without packing via ACG floorplans

Jia Wang^*, Hai Zhou

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a representation sharing the advantage of adjacency graphs. As most edges in an ACG are between modules that are close to each other, the physical -distance of two modules can be measured without packing by the shortest path between them on the ACG. Experimental results verified this relationship and possible approaches for interconnect planning are discussed.

Original language	English (US)
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1152-1155
Number of pages	4
ISBN (Print)	0780387368, 9780780387362
DOIs	https://doi.org/10.1145/1120725.1120928
State	Published - 2005
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: Jan 18 2005 → Jan 21 2005

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2

Other

Other	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/Territory	China
City	Shanghai
Period	1/18/05 → 1/21/05

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1145/1120725.1120928

Cite this

Wang, J., & Zhou, H. (2005). Interconnect estimation without packing via ACG floorplans. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 1152-1155). [1466545] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1120725.1120928

@inproceedings{bc57c23724eb4853899710df743e9eba,

title = "Interconnect estimation without packing via ACG floorplans",

abstract = "ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a representation sharing the advantage of adjacency graphs. As most edges in an ACG are between modules that are close to each other, the physical -distance of two modules can be measured without packing by the shortest path between them on the ACG. Experimental results verified this relationship and possible approaches for interconnect planning are discussed.",

author = "Jia Wang and Hai Zhou",

year = "2005",

doi = "10.1145/1120725.1120928",

language = "English (US)",

isbn = "0780387368",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1152--1155",

booktitle = "Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005",

address = "United States",

note = "2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 ; Conference date: 18-01-2005 Through 21-01-2005",

}

Wang, J & Zhou, H 2005, Interconnect estimation without packing via ACG floorplans. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466545, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 1152-1155, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 1/18/05. https://doi.org/10.1145/1120725.1120928

Interconnect estimation without packing via ACG floorplans. / Wang, Jia; Zhou, Hai.
Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc., 2005. p. 1152-1155 1466545 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Interconnect estimation without packing via ACG floorplans

AU - Wang, Jia

AU - Zhou, Hai

PY - 2005

Y1 - 2005

N2 - ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a representation sharing the advantage of adjacency graphs. As most edges in an ACG are between modules that are close to each other, the physical -distance of two modules can be measured without packing by the shortest path between them on the ACG. Experimental results verified this relationship and possible approaches for interconnect planning are discussed.

AB - ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a representation sharing the advantage of adjacency graphs. As most edges in an ACG are between modules that are close to each other, the physical -distance of two modules can be measured without packing by the shortest path between them on the ACG. Experimental results verified this relationship and possible approaches for interconnect planning are discussed.

UR - http://www.scopus.com/inward/record.url?scp=57849102356&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=57849102356&partnerID=8YFLogxK

U2 - 10.1145/1120725.1120928

DO - 10.1145/1120725.1120928

M3 - Conference contribution

AN - SCOPUS:57849102356

SN - 0780387368

SN - 9780780387362

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 1152

EP - 1155

BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

Y2 - 18 January 2005 through 21 January 2005

ER -

Interconnect estimation without packing via ACG floorplans

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this