Invited: Algorithm and Hardware Co-Design for Energy-Efficient Neural SLAM

Lingyi Huang, Cheng Yang, Yu Gong, Yang Sui, Xiao Zang, Anthony Goeckner, Qi Zhu*, Bo Yuan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we introduce a novel approach to enhancing neural network-based Simultaneous Localization and Mapping (SLAM) through the integration of model compression techniques and customized hardware architecture that focuses on micro-architectural and dataflow optimizations to improve computational efficiency and performance. Experiments across different scenarios demonstrate that the proposed approach achieves significant improvement.

Original languageEnglish (US)
Title of host publicationProceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798400706011
DOIs
StatePublished - Nov 7 2024
Event61st ACM/IEEE Design Automation Conference, DAC 2024 - San Francisco, United States
Duration: Jun 23 2024Jun 27 2024

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference61st ACM/IEEE Design Automation Conference, DAC 2024
Country/TerritoryUnited States
CitySan Francisco
Period6/23/246/27/24

Funding

This work is supported in part by National Science Foundation (NSF) Awards 2239945 and 2324936.

Keywords

  • algorithm
  • Co-design
  • hardware architecture
  • robotics
  • SLAM
  • VLSI

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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