Abstract
In this paper, we introduce a novel approach to enhancing neural network-based Simultaneous Localization and Mapping (SLAM) through the integration of model compression techniques and customized hardware architecture that focuses on micro-architectural and dataflow optimizations to improve computational efficiency and performance. Experiments across different scenarios demonstrate that the proposed approach achieves significant improvement.
Original language | English (US) |
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Title of host publication | Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9798400706011 |
DOIs | |
State | Published - Nov 7 2024 |
Event | 61st ACM/IEEE Design Automation Conference, DAC 2024 - San Francisco, United States Duration: Jun 23 2024 → Jun 27 2024 |
Publication series
Name | Proceedings - Design Automation Conference |
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ISSN (Print) | 0738-100X |
Conference
Conference | 61st ACM/IEEE Design Automation Conference, DAC 2024 |
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Country/Territory | United States |
City | San Francisco |
Period | 6/23/24 → 6/27/24 |
Funding
This work is supported in part by National Science Foundation (NSF) Awards 2239945 and 2324936.
Keywords
- algorithm
- Co-design
- hardware architecture
- robotics
- SLAM
- VLSI
ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation