Abstract
In this paper, we propose a cross-layer integrated microprocessor design methodology where instructions in software programs drive the design down to the gate level netlists. Based on in-depth exploration of the dynamic timing behavior of each instruction in the program, a fully integrated design approach is proposed with ultra-dynamic clock and power management circuits and software driven design optimization approach. A cross-layer simulation environment is also introduced enabling the collaborative co-design among compiler, architecture and circuits. The proposed design methodology helps bridge the gap between software and hardware development in a conventional development cycle. Our test vehicle using ARM based processor demonstrates substantial improvement on speed and power efficiency using the proposed design methodology.
| Original language | English (US) |
|---|---|
| Title of host publication | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 894-897 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781509063895 |
| DOIs | |
| State | Published - Sep 27 2017 |
| Event | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States Duration: Aug 6 2017 → Aug 9 2017 |
Publication series
| Name | Midwest Symposium on Circuits and Systems |
|---|---|
| Volume | 2017-August |
| ISSN (Print) | 1548-3746 |
Other
| Other | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
|---|---|
| Country/Territory | United States |
| City | Boston |
| Period | 8/6/17 → 8/9/17 |
Funding
Fig. 13. Power saving benefit and the compiler opitimization effects. VI. CONCLUSION In this paper, we present a newly developed cross-layer design methodology for single issued pipeline microprocessor. The proposed Greybox design scheme creates a collaborative development flow between software and hardware developers. By incorporating timing information into instruction set and collaborating with integrated power and clock management circuitry, the dynamic timing margin from conventional design is removed leading to significant improvement on clock speed or power efficiency. A software driven optimization methodology is proposed to further take advantage of the information obtained from instruction level timing. Our demonstration on ARM v5 based microprocessor shows a up to 34% speed improvement with the proposed methodology. ACKNOWLEDGMENT This work is in part supported by NSF grants CCF-1618065 and CCF-1116610.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering