ISPLICE3: a new simulator for mixed analog/digital circuits

E. L. Acuna; J. P. Dervenis; A. J. Pagones; R. A. Saleh

ISPLICE3: a new simulator for mixed analog/digital circuits

E. L. Acuna^*, J. P. Dervenis, A. J. Pagones, R. A. Saleh

^*Corresponding author for this work

Farley Center for Entrepreneurship and Innovation

Research output: Contribution to journal › Conference article › peer-review

Abstract

A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit.

Original language	English (US)
Pages (from-to)	13.1/1-4
Journal	Proceedings of the Custom Integrated Circuits Conference
State	Published - May 1989
Event	Proceedings of the IEEE 1989 Custom Integrated Circuits Conference - San Diego, CA, SA Duration: May 15 1989 → May 18 1989

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "ISPLICE3: a new simulator for mixed analog/digital circuits",

abstract = "A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit.",

author = "Acuna, {E. L.} and Dervenis, {J. P.} and Pagones, {A. J.} and Saleh, {R. A.}",

year = "1989",

month = may,

language = "English (US)",

pages = "13.1/1--4",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the IEEE 1989 Custom Integrated Circuits Conference ; Conference date: 15-05-1989 Through 18-05-1989",

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T2 - Proceedings of the IEEE 1989 Custom Integrated Circuits Conference

AU - Acuna, E. L.

AU - Dervenis, J. P.

AU - Pagones, A. J.

AU - Saleh, R. A.

PY - 1989/5

Y1 - 1989/5

N2 - A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit.

AB - A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit.

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M3 - Conference article

AN - SCOPUS:0024665651

SN - 0886-5930

SP - 13.1/1-4

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

Y2 - 15 May 1989 through 18 May 1989

ER -

ISPLICE3: a new simulator for mixed analog/digital circuits

Abstract

ASJC Scopus subject areas

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