ISPLICE3: a new simulator for mixed analog/digital circuits

E. L. Acuna*, J. P. Dervenis, A. J. Pagones, R. A. Saleh

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review


A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit.

Original languageEnglish (US)
Pages (from-to)13.1/1-4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - May 1989
EventProceedings of the IEEE 1989 Custom Integrated Circuits Conference - San Diego, CA, SA
Duration: May 15 1989May 18 1989

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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