ISPLICE3: A new simulator for mixed analog/digital circuits

E. L. Acuna; J. P. Dervenis; A. J. Pagones; R. A. Saleh

doi:10.1109/CICC.1989.56745

ISPLICE3: A new simulator for mixed analog/digital circuits

E. L. Acuna^*, J. P. Dervenis, A. J. Pagones, R. A. Saleh

^*Corresponding author for this work

Farley Center for Entrepreneurship and Innovation

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

This paper describes a new simulator called iSPLICE3 for the analysis of mixed analog/digital circuits. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. It features a hierarchical schematic capture package called iSPI for design entry and simulation control. It also uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface and event scheduling are provided in this paper along with the results of mixed-mode simulations of a recent memory circuit.

Original language	English (US)
Article number	5726212
Pages (from-to)	13.1.1-13.1.4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1989.56745
State	Published - 1989
Event	11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 - San Diego, CA, United States Duration: May 15 1989 → May 18 1989

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/CICC.1989.56745

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title = "ISPLICE3: A new simulator for mixed analog/digital circuits",

abstract = "This paper describes a new simulator called iSPLICE3 for the analysis of mixed analog/digital circuits. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. It features a hierarchical schematic capture package called iSPI for design entry and simulation control. It also uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface and event scheduling are provided in this paper along with the results of mixed-mode simulations of a recent memory circuit.",

author = "Acuna, {E. L.} and Dervenis, {J. P.} and Pagones, {A. J.} and Saleh, {R. A.}",

year = "1989",

doi = "10.1109/CICC.1989.56745",

language = "English (US)",

pages = "13.1.1--13.1.4",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 ; Conference date: 15-05-1989 Through 18-05-1989",

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T2 - 11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89

AU - Acuna, E. L.

AU - Dervenis, J. P.

AU - Pagones, A. J.

AU - Saleh, R. A.

PY - 1989

Y1 - 1989

N2 - This paper describes a new simulator called iSPLICE3 for the analysis of mixed analog/digital circuits. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. It features a hierarchical schematic capture package called iSPI for design entry and simulation control. It also uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface and event scheduling are provided in this paper along with the results of mixed-mode simulations of a recent memory circuit.

AB - This paper describes a new simulator called iSPLICE3 for the analysis of mixed analog/digital circuits. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. It features a hierarchical schematic capture package called iSPI for design entry and simulation control. It also uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface and event scheduling are provided in this paper along with the results of mixed-mode simulations of a recent memory circuit.

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DO - 10.1109/CICC.1989.56745

M3 - Conference article

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SN - 0886-5930

SP - 13.1.1-13.1.4

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

M1 - 5726212

Y2 - 15 May 1989 through 18 May 1989

ER -

ISPLICE3: A new simulator for mixed analog/digital circuits

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