Just say no: Benefits of early cache miss determination

G. Memik, G. Reinman, W. H. Mangione-Smith

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Scopus citations

Abstract

As the performance gap between the processor cores and the memory subsystem increases, designers are forced to develop new latency hiding techniques. Arguably, the most common technique is to utilize multi-level caches. Each new generation of processors is equipped with higher levels of memory hierarchy with increasing sizes at each level. In this paper, we propose 5 different techniques that will reduce the data access times and power consumption in processors with multi-level caches. Using the information about the blocks placed into and replaced from the caches, the techniques quickly determine whether an access at any cache level will be a miss. The accesses that are identified to miss are aborted. The structures used to recognize misses are much smaller than the cache structures. Consequently the data access times and power consumption are reduced. Using the SimpleScalar simulator, we study the performance of these techniques for a processor with 5 cache levels. The best technique is able to abort 53.1% of the misses on average in SPEC2000 applications. Using these techniques, the execution time of the applications is reduced by up to 12.4% (5.4% on average), and the power consumption of the caches is reduced by as much as 11.6% (3.8% on average).

Original languageEnglish (US)
Title of host publicationProceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003
PublisherIEEE Computer Society
Pages307-316
Number of pages10
ISBN (Electronic)0769518710
DOIs
StatePublished - Jan 1 2003
Event9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003 - Anaheim, United States
Duration: Feb 8 2003Feb 12 2003

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume12
ISSN (Print)1530-0897

Other

Other9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003
CountryUnited States
CityAnaheim
Period2/8/032/12/03

Keywords

  • Computer science
  • Delay
  • Energy consumption
  • Microprocessors

ASJC Scopus subject areas

  • Hardware and Architecture

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