Abstract
In this paper we address the problem of module selection during high-level synthesis. We present a heuristic algorithm for leakage power optimization based on the maximum weight independent set problem. A dual threshold voltage (V th) technique is used to reduce leakage energy consumption in a data flow graph. Experiments are performed on a data-path dominated test suite of six benchmarks. Our approach achieves an average of 70.9% leakage power reduction, which is very close to the optimal results from an Integer Linear Programming approach.
Original language | English (US) |
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Article number | 13.2 |
Pages (from-to) | 202-207 |
Number of pages | 6 |
Journal | Proceedings - Design Automation Conference |
State | Published - Dec 1 2005 |
Event | 42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States Duration: Jun 13 2005 → Jun 17 2005 |
Keywords
- Dual-V
- High-Level Synthesis
- Leakage Power
- Optimization
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering