Leveraging nMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory

Shaodi Wang; Andrew Pan; Cecile Grezes; Pedram Khalili Amiri; Kang L. Wang; Chi On Chui; Puneet Gupta

doi:10.1109/TED.2017.2742500

Leveraging nMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory

Shaodi Wang^*, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Chi On Chui, Puneet Gupta

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability.

Original language	English (US)
Article number	8024018
Pages (from-to)	4084-4090
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	64
Issue number	10
DOIs	https://doi.org/10.1109/TED.2017.2742500
State	Published - Oct 2017

Keywords

Magnetic random access memory (MRAM)
negative differential resistance
read disturbance
read margin
readout circuits
reliability
resistive memory
write termination

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2017.2742500

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title = "Leveraging nMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory",

abstract = "We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability.",

keywords = "Magnetic random access memory (MRAM), negative differential resistance, read disturbance, read margin, readout circuits, reliability, resistive memory, write termination",

author = "Shaodi Wang and Andrew Pan and Cecile Grezes and {Khalili Amiri}, Pedram and Wang, {Kang L.} and Chui, {Chi On} and Puneet Gupta",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

year = "2017",

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language = "English (US)",

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T1 - Leveraging nMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory

AU - Wang, Shaodi

AU - Pan, Andrew

AU - Grezes, Cecile

AU - Khalili Amiri, Pedram

AU - Wang, Kang L.

AU - Chui, Chi On

AU - Gupta, Puneet

PY - 2017/10

Y1 - 2017/10

N2 - We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability.

AB - We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability.

KW - Magnetic random access memory (MRAM)

KW - negative differential resistance

KW - read disturbance

KW - read margin

KW - readout circuits

KW - reliability

KW - resistive memory

KW - write termination

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JO - IEEE Transactions on Electron Devices

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Leveraging nMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory

Abstract

Keywords

ASJC Scopus subject areas

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