Low Power Correlating Caches for Network Processors

We introduce a new cache architecture that can be used to increase performance and reduce energy consumption in Network Processors. This new architecture is based on the observation that there is a strong correlation between different memory accesses. If a load X precedes load Y at any instance in the execution, there is a high probability that load X precedes load Y during rest of the following iterations. More importantly, we have discovered that there is a strong correlation between the source address of a load X and load Y, when they are two consecutively executed load operations, i.e., the offset between these source addresses remains usually constant between different iterations. This information is utilized by building a correlating cache architecture. The architecture consists of a Dynamic Correlation Extractor, a Correlation History Table, and a Correlation Buffer. When the architecture captures the correlating loads, it calculates the next address based on the previous offsets observed and starts prefetching these blocks. We first show simulation results investigating the frequency of correlating loads. Then, we evaluate our architecture performance using SimpleScalar/ARM simulator. For a set of representative applications, the correlating cache architecture is able to reduce the average data access time by as much as 52.7% and 36.1% on average, while reducing the energy consumption of the caches by as much as 49.2% and 25.7% on average.